Non-Planar SCR With Parallel Fin Paths for Low-Voltage ESD Protection
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Solution Overview
Problem
Conventional Silicon Controlled Rectifiers (SCRs) in non-planar technologies suffer from high turn-on and holding voltages, poor bipolar efficiency, and weak regenerative feedback, making them inadequate for efficient Electrostatic Discharge (ESD) protection in System on Chip (SoC) applications, especially in low voltage-high speed I/O and RF pads, due to current crowding and self-heating issues.
Innovation Solution
A novel SCR design with a parallel trigger path using fin-shaped or nanowire structures that bypasses the conventional base-emitter junction, providing independent forward bias current conduction and reducing trigger and holding voltages, along with nanostructures and shallow trench isolation to prevent current crowding, resulting in a device with sub-3V trigger and holding voltage and enhanced ESD robustness per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SCR design is used in non-planar technologies, then ESD protection is provided, but trigger voltage and holding voltage become very high
Solution Approach 1:
The SCR structure is segmented into multiple fins distributed across the substrate, with each fin acting as an independent current conduction path. This segmentation allows the total ESD current to be distributed across multiple parallel paths, reducing the current density and self-heating in each individual fin, thereby enabling lower trigger and holding voltages while maintaining robust ESD protection capability.
Solution Approach 2:
The patent introduces localized doping regions (n+ and p+ regions) at specific positions within the fin structures to create localized high-field regions that facilitate carrier injection and reduce the turn-on voltage. The non-uniform doping profile creates optimal conditions for reducing trigger voltage without compromising the overall ESD protection performance.
2Reliability
If conventional SCR design is used in non-planar technologies, then ESD protection is provided, but bipolar efficiency and regenerative feedback become poor
Solution Approach 1:
The SCR is divided into multiple fins that provide parallel current conduction paths, enhancing the regenerative feedback mechanism by creating multiple feedback loops. This segmentation improves bipolar efficiency by distributing the current flow and reducing self-heating effects that degrade carrier multiplication, thereby strengthening the regenerative feedback essential for low-voltage operation.
Solution Approach 2:
The fin structures are nested within the substrate with multiple fins arranged in a compact configuration, maximizing the use of available space while maintaining effective current conduction paths. This nested arrangement allows for improved bipolar efficiency by ensuring proper spatial distribution of the p-n-p-n structure components.
3Reliability
If conventional SCR design is used, then ESD protection is provided, but current crowding and self-heating issues occur
Solution Approach 1:
The SCR structure is segmented into multiple fins distributed across the substrate, with each fin acting as an independent current conduction path. This segmentation allows the total ESD current to be distributed across multiple parallel paths, reducing the current density and self-heating in each individual fin, thereby enabling lower trigger and holding voltages while maintaining robust ESD protection capability.
Solution Approach 2:
The patent transitions from a planar SCR structure to a three-dimensional fin structure, utilizing the vertical dimension to create multiple current conduction paths. This dimensional change allows for better heat dissipation and reduced current crowding by distributing the current flow across multiple spatial locations, effectively managing thermal effects during ESD events.
4Ease of manufacture
If conventional planar SCR design is deployed to non-planar technologies, then device structure is maintained, but technological limitations prevent effective operation
Solution Approach 1:
The patent adapts the SCR design from a static planar structure to a dynamic three-dimensional fin structure that can be fabricated using standard non-planar CMOS processes. The fin structures can be dynamically adjusted in terms of their dimensions, spacing, and doping profiles to optimize performance for specific technology nodes, enabling effective ESD protection in advanced non-planar technologies while maintaining manufacturing compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed SCR design achieves efficient and robust ESD protection with three times better ESD robustness per unit area, low trigger and holding voltage, and compatibility with standard process flows, while maintaining low on-resistance and no added capacitive loading.
Implementation Method 1
The SCR device of FIG. 2 does not provide options for tuning its trigger or holding voltage
Implementation Method 2
A novel SCR design with a parallel trigger path using fin-shaped or nanowire structures that bypasses the conventional base-emitter junction, providing independent forward bias current conduction
Implementation Method 3
along with nanostructures and shallow trench isolation to prevent current crowding, resulting in a device with sub-3V trigger and holding voltage and enhanced ESD robustness per unit area
Data Source
AI summary
The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.