Non-Planar Transistor Channel Height Control via Isolation Regions
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Solution Overview
Problem
Integrated circuit (IC) structures incorporating non-planar multi-gate field effect transistors (MUGFETs) face challenges in achieving optimal circuit performance due to the need for varying drive currents, which is currently addressed by using multiple semiconductor fins of different heights, leading to increased chip area and performance variations.
Innovation Solution
A method of forming IC structures with MUGFETs having different effective channel widths by selectively removing sacrificial gates to create gate openings, followed by additional processing steps such as forming isolation regions or using protective sacrificial materials to ensure varying channel region heights and drive currents, without increasing chip size or causing performance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If semiconductor fins of different heights are used to achieve different drive currents, then the drive current requirements are met, but the manufacturing complexity increases and performance variations occur
Solution Approach 1:
The patent applies local quality by forming isolation regions at specific locations within the channel region of certain FETs. This creates localized modifications that reduce the effective channel height in targeted areas, allowing different FETs to have different drive currents without requiring different fin heights across the entire structure. The isolation regions are formed only where needed to achieve the desired current characteristics.
Solution Approach 2:
The patent uses preliminary action by forming sacrificial gates before the final gate structure, which are then selectively removed to create openings. These openings allow subsequent formation of isolation regions or recesses in the channel. This preliminary structuring enables precise control over channel height variations while maintaining uniform fin formation across all devices.
2Power
If multiple semiconductor fins are used to increase effective channel width, then the drive current is improved, but the chip area increases
Solution Approach 1:
The patent transitions from controlling drive current through horizontal dimension (number of fins or channel width) to controlling it through vertical dimension (channel height via isolation regions). By modifying the effective channel height in the vertical dimension rather than increasing channel width horizontally, the patent achieves different drive currents without increasing chip area.
3Power
If semiconductor fins with different heights are used, then different drive currents are achieved, but downstream processing is impacted and performance variations occur
Solution Approach 1:
The patent maintains uniform fin heights across all FETs for consistent downstream processing, then introduces local variations through isolation regions formed only in specific FET channel regions. This localized approach achieves the necessary drive current differentiation while preserving the uniformity of the overall fin structure, ensuring consistent processing and reduced performance variations.
Data Source
AI summary
Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material. Also disclosed is an IC structure formed according to the method.