Non-Planar Transistor Doping via Selective Epitaxial Growth
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Solution Overview
Problem
The fabrication of non-planar transistors faces challenges in forming metal semiconductor contacts with low contact resistance due to non-uniform doping and residual defects in 3-D structures, which affect the Schottky barrier height and lead to poor silicide formation and leakage currents.
Innovation Solution
The use of an epitaxial process for uniformly controlled doping in non-planar structures, where a doped semiconductor layer is grown using selective epitaxial growth, and a metal silicide layer is formed to reduce the Schottky barrier height by segregating dopant atoms, thereby minimizing series resistance and preventing residual defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional implantation methods are used to dope non-planar structures, then doping can be performed during or after source/drain implantation, but the doping becomes non-uniform and residual defects are introduced that result in poor silicide formation and leakage currents
Solution Approach 1:
The patent replaces the mechanical implantation process with a chemical epitaxial growth process. Instead of physically implanting dopants into the non-planar structure, dopant atoms are incorporated during the selective epitaxial growth of semiconductor material, achieving uniform doping without the defects associated with implantation methods
Solution Approach 2:
The patent changes the doping parameter from post-growth implantation to in-situ doping during epitaxial growth. This parameter change enables uniform dopant distribution throughout the grown layer while avoiding the residual defects that plague implantation-based approaches
2Reliability
If implantation is used to increase doping level for reducing Schottky barrier height, then contact resistance can be reduced, but residual defects are left that result in poor silicide formation and leakage currents
Solution Approach 1:
The patent substitutes the mechanical implantation process with chemical epitaxial growth for doping. This replacement eliminates the residual defects caused by implantation while achieving the necessary high doping levels for low Schottky barrier height and low contact resistance
Solution Approach 2:
The patent uses epitaxial growth as an intermediary process that incorporates dopants uniformly during material formation. This intermediary approach avoids direct implantation into the finished structure, preventing defect generation while achieving the required doping levels for low contact resistance
3Ease of manufacture
If conventional planar structures are used, then fabrication is simpler, but gate control of the channel is insufficient and areal density is lower
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional non-planar structures with selective epitaxial growth. This dimensional change enables better gate control through vertical channel formation and increased areal density while maintaining fabrication feasibility through selective growth processes
Solution Approach 2:
The patent applies selective epitaxial growth to create locally differentiated regions with different doping levels and structures. This local quality approach enables optimized gate control in the channel region while maintaining simplicity in other areas of the device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of non-planar transistors with low Schottky barrier height and ultra-shallow junctions, improving short channel effects and reducing series resistance, thus addressing the limitations in scaling traditional transistors.
Implementation Method 1
a doped semiconductor layer is grown using selective epitaxial growth
Implementation Method 2
a metal silicide layer is formed to reduce the Schottky barrier height by segregating dopant atoms
Data Source
AI summary
Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.