Non-Planar Transistor Fin Structure with Concave Profile
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Solution Overview
Problem
Conventional planar transistors fail to meet the requirements of miniaturized electronic products due to issues such as uneven voltage distribution and leakage current in non-planar Fin-FETs, which are exacerbated by the three-dimensional structure.
Innovation Solution
A non-planar transistor design featuring a fin structure with a concave portion and a novel spacer structure, where the first spacer is taller than the second spacer, is used to avoid leakage current and control the semiconductor layer's shape and size, enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional Fin-FET with 90-degree corner structure is used, then the device can be manufactured with standard processes, but leakage current increases and voltage distribution becomes uneven
Solution Approach 1:
The patent applies curvature by replacing the conventional 90-degree corner structure with a rounded corner structure. The rounded corners eliminate sharp edges that cause high electric field concentration, thereby reducing leakage current while maintaining manufacturability through standard fabrication processes that can accommodate curved profiles.
Solution Approach 2:
The patent implements local quality by modifying only the corner regions of the fin structure while keeping the main body structure intact. The rounded corners create localized regions with different electrical properties that improve voltage distribution without requiring complete restructuring of the entire device.
2Device complexity
If a conventional Fin-FET with 90-degree corner structure is used, then the device structure is simple, but voltage distribution through the channel becomes uneven
Solution Approach 1:
The rounded corner structure smooths the electric field distribution across the channel by eliminating sharp geometric transitions. This curvature modification creates a more uniform potential gradient through the channel, improving voltage distribution while adding minimal structural complexity.
3Volume of moving object
If planar transistors are used for miniaturization, then device size is reduced, but they fail to meet high integration and high performance requirements
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to three-dimensional Fin-FET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area without proportionally increasing the footprint area, enabling higher integration density while maintaining or improving electrical performance through enhanced current drive capability.
Data Source
AI summary
A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a first spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The fin structure includes an upper portion, a concave portion and a lower portion, and the concave portion is disposed between the upper portion and the lower portion. The first spacer structure is disposed on a sidewall of the gate structure. The first spacer structure includes a first spacer and a second spacer, wherein the first spacer is disposed between the second spacer, and a height of the first spacer is different from a height of the second spacer. The source/drain region is disposed in a semiconductor layer at two sides of the first spacer structure.