Non-Planar Transistor Strain Induction via Segmented Epitaxy
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Solution Overview
Problem
Implementing compressive strain in non-planar tri-gate transistors is challenging due to the lack of confinement for the strain material, which affects carrier mobility enhancement in p-type MOSFETs.
Innovation Solution
The process involves forming a semiconductor body with a silicon fin, depositing a gate dielectric and electrode layers, creating trenches for strain material deposition, and using epitaxial silicon germanium to induce compressive strain within the channel region by confining it with silicon pillars, ensuring hydrostatic pressure is applied.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial deposition of Si1-xGex is used to create compressive strain in non-planar transistors, then hole mobility enhancement is achieved, but the strain material lacks confinement affecting the strain effectiveness
Solution Approach 1:
The source/drain region is segmented into multiple portions with different materials: a first portion containing Si1-xGex for compressive strain and a second portion for tensile strain. This segmentation allows independent optimization of strain characteristics in different regions, achieving effective carrier mobility enhancement while maintaining proper strain material confinement through selective placement.
Solution Approach 2:
Different strain characteristics are applied to different local regions: compressive strain (Si1-xGex) in the first portion and tensile strain in the second portion. This local quality approach ensures that each region receives the appropriate strain type for optimal hole and electron mobility enhancement respectively, resolving the confinement issue by targeting strain application precisely where needed.
2Reliability
If a conformal silicon nitride-capping layer is deposited to induce tensile strain, then electron mobility enhancement is achieved, but this approach does not effectively create compressive strain for hole mobility enhancement
Solution Approach 1:
The transistor structure is divided into n-type and p-type regions with different strain implementations. The n-type region uses conformal silicon nitride-capping layer for tensile strain to enhance electron mobility, while the p-type region uses selective epitaxial deposition of Si1-xGex for compressive strain to enhance hole mobility. This segmentation enables both strain types to coexist in the same device structure.
Solution Approach 2:
The transistor employs composite material strategies: silicon nitride-capping layer for tensile strain in n-type regions and Si1-xGex alloy for compressive strain in p-type regions. This composite approach allows the device to achieve both electron and hole mobility enhancement through appropriate material selection for each carrier type region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively enhances carrier mobility in non-planar tri-gate transistors by realizing compressive strain in the channel region, improving transistor performance and reducing short-channel effects.
Implementation Method 1
A strain material can be deposited and re-grown in the trenches
Implementation Method 2
confining it with silicon pillars, ensuring hydrostatic pressure is applied
Data Source
AI summary
Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a different plane relative to the substrate. The gate structure can be situated on the semiconductor body and the silicon fin and perpendicular to the semiconductor body. After formation of the semiconductor body and the gate structure on the substrate, a dielectric material can be conformally deposited on the substrate and etched to form spacers on the semiconductor body and the gate structure. The substrate can be patterned and etched to form trenches in the semiconductor body adjacent to the spacers on the gate structure. A strain material can be introduced into the trenches.