Non-Planar Transistors for High-Density STT-RAM
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Solution Overview
Problem
Conventional spin transfer torque random access memory (STT-RAM) faces challenges in scaling to higher densities due to limitations in current capacity and increased power leakage as transistor sizes shrink, making it difficult to maintain high-speed operation with low current pulses and reduce cell size.
Innovation Solution
The integration of non-planar transistors with gate oxides not lying in a single plane, such as dual gate, Fin, vertical, and round-gate transistors, which reduce leakage current and increase drain-to-source saturation current, allowing for higher write currents without increasing transistor size, enabling higher density STT-RAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional planar transistors are used to support higher write currents for high-speed operation, then switching speed is improved, but transistor gate width must increase leading to larger cell size and reduced density
Solution Approach 1:
The patent transitions from planar (2D) transistor geometry to three-dimensional non-planar transistor structures such as FinFETs, nanosheet FETs, and vertical channel transistors. This dimensional change increases the effective channel area and drive current capability without increasing the planar footprint, thereby maintaining high switching speeds while reducing cell size and increasing storage density.
Solution Approach 2:
The patent employs nested or stacked transistor configurations where multiple active channels are vertically integrated within a compact footprint. This allows multiple current paths to be contained within a single planar area, effectively multiplying the current capacity without proportionally increasing the cell area, thus resolving the contradiction between speed and density.
2Area of moving object
If transistor size is reduced to increase storage density, then cell size decreases, but leakage current increases and drive current capability decreases
Solution Approach 1:
By moving to three-dimensional transistor structures with vertical channels and suspended gates, the patent achieves better electrostatic control over the channel at scaled dimensions. This enhanced control reduces off-state leakage current while maintaining compact cell sizes, directly addressing the leakage problem associated with conventional planar transistor scaling.
Solution Approach 2:
The patent modifies key transistor parameters including channel orientation (vertical vs. horizontal), gate positioning (suspended, wrap-around, or side-gate configurations), and interface geometry to optimize the balance between drive current and leakage current. These parameter changes enable dense scaling while maintaining low leakage and sufficient drive capability through improved electrostatic control.
3Ease of manufacture
If conventional planar transistors are used with scaled dimensions, then manufacturing is simplified, but power leakage becomes unacceptable and drive current is insufficient
Solution Approach 1:
The patent introduces three-dimensional transistor architectures that, while more complex than planar devices, leverage established semiconductor fabrication techniques adapted for vertical structures. The manufacturing complexity is managed through sequential processing steps that build 3D features using modified 2D lithography and deposition, achieving acceptable power leakage performance without requiring entirely new fabrication paradigms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the development of higher density STT-RAM with improved performance by supporting higher write currents with shorter pulse durations and reducing power leakage, enabling efficient scaling and operation at smaller dimensions.
Implementation Method 1
The current changes state of the conventional magnetic element 12 using the spin transfer torque switching effect
Implementation Method 2
The conventional magnetic element 12 is configured to be changeable between resistance states by driving a current through the conventional magnetic element 12. The current changes state of the conventional magnetic element 12 using the spin transfer torque switching effect.
Data Source
AI summary
A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.