Non-Planar On-Package Via Capacitor Design
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Solution Overview
Problem
The density of on-package metal-insulator-metal (MIM) capacitors is limited by available electrode surface area and the need for signal escape via vias, which restricts capacitance and increases parasitic inductance, limiting their applicability in RF and digital circuits.
Innovation Solution
A non-planar on-package via capacitor is fabricated using a Self-Assembled Monolayers (SAM) assisted Laser direct structuring process, allowing for increased plate area and reduced plate distance without increasing the capacitor's footprint, achieved through conical or cylindrical shapes with a high-k dielectric material, enhancing capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar MIM capacitor structure is used, then manufacturing is simple, but capacitance density is limited due to restricted electrode surface area
Solution Approach 1:
The patent transitions from planar (2D) electrode surfaces to three-dimensional non-planar electrode structures with increased surface area. The electrodes are formed with curved, undulating, or multi-level surfaces that extend vertically and laterally, effectively utilizing the Z-dimension to increase capacitance density without increasing the horizontal footprint of the capacitor.
Solution Approach 2:
The patent employs curved and non-planar electrode surfaces instead of flat planes. The electrodes feature curved surfaces including cylindrical, conical, or undulating geometries that increase the effective surface area for capacitance while maintaining a compact form factor, directly addressing the limitation of planar structures.
2Reliability
If large via pads are used for signal escape, then connection is reliable, but parasitic inductance increases
Solution Approach 1:
The patent moves the signal escape path from a planar via pad configuration to a three-dimensional non-planar via structure. The via is formed with tapered, curved, or multi-segment geometries that reduce the inductance by optimizing the current path through the via, while still providing reliable electrical connection to the underlying conductive layer.
Solution Approach 2:
The patent changes the geometric parameters of the via structure, including aspect ratio, taper angle, and wall curvature, to optimize the inductance characteristics. By carefully controlling these parameters during fabrication, the via achieves lower parasitic inductance while maintaining mechanical strength and electrical reliability.
3Quantity of substance
If electrode surface area is increased, then capacitance increases, but capacitor footprint increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension (Z-axis) to increase electrode surface area. Through non-planar electrode geometries with curved surfaces, multiple levels, and vertical extensions, the capacitor achieves high capacitance values while maintaining a compact horizontal footprint suitable for high-density integration.
Solution Approach 2:
The patent employs nested electrode structures where conductive layers are arranged in multiple levels and configurations within a compact vertical space. The non-planar electrodes are positioned to maximize overlapping surface area between positive and negative terminals while maintaining a small overall footprint, effectively nesting multiple capacitive elements in a compact arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases capacitance density, enabling reduced circuit size and lower parasitic inductance, thus improving frequency bandwidth and enabling high-density capacitance suitable for RF and power delivery applications.
Implementation Method 1
A non-planar on-package via capacitor is fabricated using a Self-Assembled Monolayers (SAM) assisted Laser direct structuring process
Implementation Method 2
A non-planar on-package via capacitor is fabricated using a Self-Assembled Monolayers (SAM) assisted Laser direct structuring process
Implementation Method 3
achieved through conical or cylindrical shapes with a high-k dielectric material, enhancing capacitance density
Data Source
AI summary
Embodiments are generally directed to non-planar on-package via capacitor. An embodiment of an embedded capacitor includes a first plate that is formed in a package via; a dielectric layer that is applied on the first plate; and a second plate that is formed in a cavity in the dielectric layer, wherein the first plate and the second plate are non-planar plates.