Non-Power-of-Two Burst Length Memory Logic
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Solution Overview
Problem
High-performance computing memory systems face challenges in transmitting error-detecting codes without increasing the number of I/O pins, which raises costs and introduces additional failure modes, as they typically require dedicated lines for error-detecting codes, limiting data bandwidth when incorporating non-power-of-two burst lengths.
Innovation Solution
Implementing a memory system with non-power-of-two burst length logic that extends the burst length to include error-detecting codes on data lines, allowing error-detecting codes to be transmitted within existing data bursts without additional pins, by modifying command-to-command timing and clock frequency, or utilizing existing timing bubbles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-detecting codes are transmitted using dedicated lines, then data integrity is improved, but the number of I/O pins increases, raising cost and introducing additional failure modes
Solution Approach 1:
The patent merges the transmission of error-detecting codes with the data transmission by utilizing the same data lines for both purposes. The error-detecting codes are inserted into the burst sequence on the existing data lines, eliminating the need for separate dedicated lines for error detection. This combining approach maintains data integrity while reducing the number of I/O pins required.
Solution Approach 2:
The patent introduces a temporal dimension to the transmission by inserting error-detecting codes at specific positions within the burst sequence rather than using parallel spatial lines. The error-detecting codes are transmitted during the burst cycle, utilizing time multiplexing on the same physical lines, thereby reducing pin count while maintaining reliability.
2Productivity
If power-of-two burst lengths are used, then data bandwidth is improved, but the ability to accommodate error-detecting codes without additional pins is limited
Solution Approach 1:
The patent makes the burst length dynamic by extending it from a fixed power-of-two value to a non-power-of-two value. This dynamic adjustment allows the burst length to be modified specifically to accommodate error-detecting codes within the existing data lines, maintaining compatibility with current memory interfaces while enabling error detection functionality.
Solution Approach 2:
The patent changes the burst length parameter from a power-of-two value (2, 4, 8) to a non-power-of-two value (e.g., 10). This parameter change enables the inclusion of error-detecting codes within the burst sequence on the same data lines, allowing the system to accommodate error detection without requiring additional pins or reducing data bandwidth.
3Reliability
If additional I/O pins are added for error-detecting codes, then data integrity is improved, but system cost increases and additional failure modes are introduced
Solution Approach 1:
The patent combines the error-detection function with the existing data transmission infrastructure by inserting error-detecting codes into the burst sequence on the same data lines. This merging eliminates the need for additional I/O pins, thereby avoiding the increased cost and additional failure modes that would result from adding more pins and corresponding interconnects.
Data Source
AI summary
A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.