Mapping Non-Prefetchable Storage to GMMIO Space
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Solution Overview
Problem
The increasing demand for non-prefetchable MMIO space in PCIe devices leads to a shortage of LMMIO space, limiting the number of devices that can be supported in highly scalable platforms.
Innovation Solution
Mapping non-prefetchable storage locations into GMMIO space, which is typically reserved for prefetchable storage, by ensuring that host and I/O devices are not coupled via PCIe-to-PCI/PCI-X bridges and prohibiting peer-to-peer requests from devices below such bridges, thus avoiding issues like byte-merging and silent data corruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-prefetchable storage locations are mapped into LMMIO space, then the mapping resources can be used with non-prefetchable semantics, but the limited LMMIO space (addressable via 32-bit addresses) becomes exhausted, limiting the number of PCIe devices that can be supported
Solution Approach 1:
The patent extends the mapping space from 32-bit LMMIO to 64-bit GMMIO space, effectively adding a new dimension of addressable memory space. This allows non-prefetchable storage locations to be mapped into GMMIO space using 64-bit addresses, thereby expanding the available address space from 4GB to potentially exabytes, which directly resolves the limitation on the number of supported PCIe devices
Solution Approach 2:
The patent changes the address width parameter from 32-bit to 64-bit for mapping non-prefetchable storage locations. By modifying this fundamental parameter, the available address space increases exponentially, allowing far more devices to be supported while maintaining non-prefetchable semantics through appropriate host and device configuration
2Adaptability or versatility
If non-prefetchable storage locations are mapped into GMMIO space, then more devices can be supported, but data corruption or undefined behaviors may occur due to byte-merging or silent data corruption from PCIe-to-PCI/PCI-X bridges
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a PCIe switch that properly handles 64-bit address mappings and prevents byte-merging issues. The switch acts as a mediator between the host and devices mapped into GMMIO space, ensuring that memory access requests are correctly routed and executed without corruption, thereby maintaining data integrity while enabling expanded device support
Solution Approach 2:
The patent applies preliminary anti-action by prohibiting peer-to-peer requests from devices below PCIe-to-PCI/PCI-X bridges and by configuring the host and devices to prevent byte-merging behaviors before they can cause data corruption. These preventive measures are established in advance through system configuration and protocol enforcement, eliminating potential data integrity issues before they manifest
Data Source
AI summary
A system including a host and a device. The device has at least one non-prefetchable storage location. The host and the device are configured to map the at least one non-prefetchable storage location into memory mapped input/output space that is addressed via greater than 32 address bits.