Non-Rectangular Floating Gate for Memory Programming Efficiency
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Solution Overview
Problem
Conventional non-volatile memory bit cells face challenges in programming efficiency, which scales with device size, leading to larger device sizes and increased fabrication complexity due to the need for additional implantation masks to optimize cell junctions.
Innovation Solution
A non-volatile memory bit cell structure featuring a field-effect transistor with a non-rectangular shaped gate electrode and a shared floating gate with a capacitor, optimized through shallow trench isolation and dopant implantations, enhancing programming efficiency while reducing bit cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional rectangular gate electrodes are used, then fabrication processes are simpler, but programming efficiency is poor and device size increases
Solution Approach 1:
The patent applies asymmetry by designing the gate electrode with a non-rectangular shape, specifically with different widths at different positions along the channel length. This asymmetric geometry creates non-uniform electric field distribution that enhances hot carrier generation and improves programming efficiency, while resolving the contradiction between programming efficiency and geometric complexity.
Solution Approach 2:
The patent implements local quality by varying the gate electrode width at specific locations along the channel. The gate electrode has different widths in different regions, creating localized electric field enhancements where needed to improve programming efficiency without requiring complex additional structures throughout the entire device.
2Productivity
If device size is increased to improve programming efficiency, then programming efficiency improves, but device area increases
Solution Approach 1:
The patent changes the geometric parameters of the gate electrode, specifically the width-to-length ratio at different positions, to optimize programming efficiency. By adjusting these dimensional parameters rather than simply scaling up the entire device, the patent achieves improved programming efficiency while maintaining a compact bit cell area.
3Productivity
If additional implantation masks are used to optimize cell junctions, then programming efficiency improves, but fabrication complexity increases
Solution Approach 1:
The patent extracts the programming efficiency enhancement from the implantation process and embeds it directly into the gate electrode geometry. By incorporating the optimization function into the gate structure itself rather than relying on additional implantation masks, the patent simplifies the fabrication process while maintaining improved programming efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure improves programming efficiency and enables smaller bit cell sizes by leveraging channel hot carrier effects and optimized gate electrode geometry, simplifying fabrication processes.
Implementation Method 1
The structure improves programming efficiency and enables smaller bit cell sizes by leveraging channel hot carrier effects and optimized gate electrode geometry
Implementation Method 2
The structure further includes a capacitor having a second gate electrode. The second gate electrode is coupled to the first gate electrode to define a floating gate
Data Source
AI summary
Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape.