Non-segregated Core Memory Cells as Drain-side Select Gates
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Solution Overview
Problem
Existing memory devices face reliability issues due to variations in select gate devices across sub-blocks, caused by fixed threshold voltages in NMOS transistors, leading to inconsistencies in data storage when physical segregation of select gate devices is not feasible.
Innovation Solution
Implementing non-segregated core memory cells as drain-side select gates with programmable threshold voltages, allowing for shared control signals and precise tuning of select gate devices in logical select gate layers, while using segregated NMOS transistors at the source-side for activation control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS transistors with fixed threshold voltages are used as select gate devices, then device simplicity is maintained, but reliability deteriorates due to variations across sub-blocks
Solution Approach 1:
The memory array is divided into multiple sub-blocks, each with its own select gate devices. This segmentation allows independent control and threshold voltage tuning for each sub-block, eliminating the reliability issues caused by variations across sub-blocks while maintaining overall device functionality.
Solution Approach 2:
The patent replaces NMOS transistors with fixed threshold voltages with core memory cells that have programmable threshold voltages. This parameter change enables precise tuning of select gate characteristics for each sub-block, significantly improving data storage consistency and reliability.
2Reliability
If physical segregation of select gate devices is implemented, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent uses core memory cells that can be programmed to replicate the functionality of segregated select gate devices. By programming threshold voltages into these cells, the system achieves the reliability benefits of physical segregation without the manufacturing complexity, as the logical segregation is achieved through programming rather than physical separation.
3Ease of manufacture
If non-segregated core memory cells are used as drain-side select gates, then manufacturing ease improves, but threshold voltage precision deteriorates
Solution Approach 1:
The patent utilizes the programmable nature of core memory cells to achieve precise threshold voltage control. By applying specific programming voltages during manufacturing and operation, the system can precisely tune the threshold voltages of non-segregated select gate devices, overcoming the precision limitations while maintaining manufacturing simplicity.
Data Source
AI summary
Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.