Non-Shared Metal Gate GAA Transistors for pFET Isolation
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Solution Overview
Problem
Current GAA transistor fabrication techniques face challenges in forming high-quality work function metals, particularly in CMOS devices, due to patterning constraints, leading to weakened pFET performance as the thin pWFM cannot completely shield the impact of the complementary nWFM.
Innovation Solution
The method involves forming non-shared metal gate integration in GAA transistors by creating distinct work function metal stacks for nFET and pFET, with no shared work function metal stacks between the two, while sharing gate dielectrics, to isolate pFET from deleterious effects caused by nWFM, thereby improving pFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared work function metal stacks are used between nFET and pFET, then device complexity is reduced, but pFET performance deteriorates due to interference from nWFM
Solution Approach 1:
The gate stack is segmented into separate work function metal regions for nFET and pFET. The method forms a first work function metal stack in the first region and a second work function metal stack in the second region, preventing the nFET work function metal from interfering with pFET performance while maintaining manageable device complexity through systematic separation.
Solution Approach 2:
Different work function metal stacks are implemented in different regions of the device. The first work function metal stack is optimized for nFET operation in the first region, while the second work function metal stack is optimized for pFET operation in the second region, allowing each region to have tailored electrical characteristics without mutual interference.
2Manufacturing precision
If thin pWFM is used to meet patterning constraints, then manufacturing precision is improved, but shielding effectiveness deteriorates allowing nWFM impact to weaken pFET performance
Solution Approach 1:
The work function metal structure is divided into spatially separated first and second stacks. This segmentation ensures that the thin pWFM in the pFET region provides adequate shielding against nWFM interference while meeting patterning constraints, as each stack can be independently optimized for its specific function without relying on continuous metal coverage.
Data Source
AI summary
Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.