Non-Shared Page Tables for Accelerator Memory Sharing
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Solution Overview
Problem
Existing mechanisms for sharing memory between a main CPU and accelerator devices, such as DMA and GART, face limitations including memory fragmentation, complexity in modern multi-threading environments, and security concerns, requiring prior knowledge of memory locations and restrictive configurations.
Innovation Solution
The system employs non-shared and shared page tables managed by a kernel mode device driver to allow accelerator devices to access physical memory independently, enabling them to operate in virtual memory address spaces and share system memory with CPU processor cores, with mechanisms for handling page faults and memory management independently of the main OS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DMA controllers are used to share memory between CPU and accelerator devices, then memory sharing capability is improved, but device complexity and configuration burden increase
Solution Approach 1:
The patent extracts the memory management function from the main OS by creating a separate memory manager in the accelerator device. This independent memory manager handles its own page tables and memory allocation, eliminating the need for complex OS configuration and intervention in DMA operations.
Solution Approach 2:
The accelerator device's memory manager autonomously manages memory allocation, page table creation, and DMA operations without requiring OS services. The system performs self-service by independently handling memory sharing tasks that would otherwise require complex OS coordination and configuration.
2Adaptability or versatility
If scatter-gather DMA transfers are used to handle memory fragmentation, then adaptability to fragmented memory is improved, but processing time and complexity increase
Solution Approach 1:
The patent segments the memory management function into separate page tables managed by the accelerator device. Each page table independently manages memory segments, allowing the system to handle fragmentation efficiently without requiring complex scatter-gather operations or linked-list mechanisms.
Solution Approach 2:
The memory manager dynamically creates and updates page tables as needed, allowing flexible adaptation to memory fragmentation without fixed configuration requirements. The dynamic page table management enables efficient handling of fragmented memory regions without increasing processing time.
3Productivity
If page tables are shared between OS and accelerator device, then memory management efficiency is improved, but security and isolation concerns worsen
Solution Approach 1:
The patent segments page tables into separate structures: OS page tables for CPU processes and accelerator device page tables for memory access. This segmentation maintains security and process isolation while enabling efficient memory sharing between the accelerator device and physical memory through independent but coordinated page table management.
Data Source
AI summary
Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.