Non-shrinkable IP Integration via Scale Simulation
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Solution Overview
Problem
Conventional methods for shrinking integrated circuits face challenges in maintaining the original dimensions and performance of non-shrinkable circuits, such as analog and high-speed circuits, when integrated with shrinkable circuits, leading to performance drift and increased handling time due to grid snapping and hierarchical GDS file flattening.
Innovation Solution
A method involving the simulation of non-shrinkable circuits at a reduced scale, followed by blowing up their GDS layout, flattening, and integrating it with shrinkable circuits, while adjusting critical dimensions and relocating contacts/vias to maintain original sizes and locations, ensuring accurate performance matching across technology generations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-shrinkable circuits are magnified and then shrunk using conventional GDS layout methods, then they can be integrated with shrinkable circuits, but the resulting dimensions and locations may not be exactly the same as the original design due to grid snapping, causing performance drift
Solution Approach 1:
The patent applies preliminary action by performing simulation at the reduced scale before final layout generation. The method simulates the non-shrinkable circuit at the reduced scale to determine accurate dimensions and locations, then uses these pre-calculated values in the blown-up GDS layout. This preliminary simulation step ensures that when the layout is subsequently shrunk, the circuits land precisely on grid points without performance drift, resolving the dimensional accuracy issue while maintaining integration capability.
2Reliability
If GDS files are flattened into the same level to avoid broken lines caused by snapping, then hierarchical structure is lost, but handling time such as post-layout simulation time is significantly increased
Solution Approach 1:
The patent applies segmentation by dividing the GDS file handling into two separate processes: (1) generating the blown-up GDS layout with hierarchical structure preserved for manual editing and inspection, and (2) generating a separate abstract file containing only the necessary circuit data for simulation. This segmentation allows the hierarchical structure to be maintained in the layout file while avoiding the time penalty of flattening, as the simulation process uses the optimized abstract file instead. The method thus maintains layout integrity while significantly reducing handling time.
3Reliability
If non-shrinkable circuits are kept at original size while shrinkable circuits are downscaled, then performance of non-shrinkable circuits is maintained, but size and location mismatches occur between contacts and vias
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the scale factor based on the circuit type. For non-shrinkable circuits, the scale factor is set to 1.0 (no scaling), while for shrinkable circuits, the scale factor is less than 1.0 (downscaling). The method automatically detects circuit boundaries and applies appropriate scaling parameters to each region. Additionally, the blown-up GDS layout is generated with compensation parameters that pre-calculate the correct positions and sizes of contacts and vias, ensuring they align perfectly with the non-shrinkable circuits even after the overall shrunk scale is applied to the integrated design.
Data Source
AI summary
A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.