Non-speculative Store Coalescing via Atomic Groups

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Solution Overview

Problem

Multiprocessor systems employing the Total Store Order (TSO) memory consistency model face challenges in coalescing store operations without violating the strict store order, leading to deadlocks and livelocks when attempting to write all stores atomically, as existing solutions require speculation or centralized resources.

Innovation Solution

Implementing a non-speculative approach by forming atomic groups of store instructions and writing them in lexicographical order, where each cacheline is written immediately if permission is held, and conflicts are resolved by delaying external requests until the atomic group is complete, avoiding deadlocks and livelocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If store operations are coalesced in TSO systems to improve performance, then store buffer capacity pressure is reduced and write operations are minimized, but store order violations occur leading to deadlocks and livelocks

Engineering Contradiction:
Improvestore coalescing performanceVSAvoidstore order compliance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments store operations into atomic groups that are coalesced and written atomically to memory. By dividing the store buffer into multiple atomic groups and managing them independently, the system achieves coalescing benefits while maintaining TSO compliance through controlled atomicity boundaries.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by acquiring permissions for all cachelines in an atomic group before writing any of them. This preliminary permission acquisition ensures that when writes occur, they maintain proper ordering and atomicity, preventing deadlocks and livelocks while enabling coalescing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If atomic groups of stores are written to memory, then TSO compliance is maintained, but permission acquisition delays occur when conflicts are detected

Engineering Contradiction:
ImproveTSO complianceVSAvoidpermission acquisition delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary permission acquisition for all cachelines in an atomic group before executing writes. This advance preparation prevents mid-write conflicts and ensures atomicity, reducing overall delays by avoiding rollback scenarios.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts permission acquisition strategies based on conflict detection. When conflicts are detected during permission acquisition, the system adapts by delaying external requests until the atomic group is complete, optimizing performance while maintaining correctness.

Inventive Principle:
Principle #15Dynamics

3Productivity

If speculative relaxation of memory order operations is used to accommodate store buffers, then store buffer performance is improved, but system complexity increases due to buffered history and rollback requirements

Engineering Contradiction:
Improvestore buffer performanceVSAvoidbuffered history management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the complexity of speculation and rollback by implementing a non-speculative approach. Instead of buffering history and performing rollbacks, the system directly writes atomic groups to memory in TSO-compliant order, eliminating the need for complex speculative management infrastructure.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system achieves store buffer performance improvement through self-service mechanisms where atomic groups are automatically formed and written without external speculation management. The store buffer autonomously handles coalescing and atomic writes, reducing system complexity while maintaining performance.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11119920B2Systems and methods for non-speculative store coalescing and generating atomic write sets using address subsets
Publication Date: 2021.09.14 ARRAY CACHE TECHNOLOGIES LLC
  • US11119920B2 patent drawing
  • US11119920B2 patent drawing
  • US11119920B2 patent drawing

AI summary

A method for performing store buffer coalescing in a multiprocessor computer system includes forming, in a coalescing store buffer associated with a core in said multiprocessor system, an atomic group of writes; and performing each individual write in said atomic group in an order which is a function of an address in a memory system to which each of the writes in said atomic group are being written.