Non-uniform Bus Interconnect for Tiled Last Level Cache
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Solution Overview
Problem
Current cache memory systems for multi-CPU and multi-LLC memory bank systems face challenges in achieving low-power consumption, mid-range complexity, and mid-range bandwidth while maintaining tile-ability and scalability, particularly in mobile device CPU systems with 1 to 8 nodes, as existing solutions either consume high power or lack scalability.
Innovation Solution
A non-uniform bus (NUB) interconnect protocol with dedicated data channels for each memory transaction type, each channel equipped with arbitration multiplexors and operating independently, allowing unique latency, bandwidth, and stall protocols for read and write transactions, eliminating the need for cross-channel awareness and content addressable memory, and enabling tile-able modular design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If full ring busses, meshes or direct end-to-end wires are used for interconnect, then high bandwidth is achieved, but wire cost, area requirements, power consumption and system complexity increase exponentially
Solution Approach 1:
The interconnect network is segmented into multiple independent data channels, each dedicated to specific memory transaction types (read requests, write requests, read responses, write responses). This segmentation allows each channel to be optimized independently and reduces the complexity of managing a single high-bandwidth interconnect by dividing it into multiple specialized lower-complexity channels that operate in parallel.
2Productivity
If high-complexity solutions like rings and meshes are used, then high bandwidth is achieved, but power consumption increases
Solution Approach 1:
Each data channel is assigned a specific function (read requests, write requests, read responses, write responses) with locally optimized characteristics. This allows the system to use higher bandwidth channels only where needed for specific transaction types while using simpler, lower-power channels for other transactions, rather than provisioning all channels at maximum bandwidth capability.
3Use of energy by moving object
If dedicated data channels with independent operation are implemented, then power consumption is reduced, but system complexity increases
Solution Approach 1:
Multiple data channels are merged into a single tiled last level cache structure that shares common control logic and arbitration mechanisms. The arbitration multiplexors and tileable modular design allow independent channels to be coordinated through unified control, reducing the overall system complexity despite having multiple dedicated channels.
4Adaptability or versatility
If LLC memory banks are designed to be tile-able and modular, then scalability is improved, but achieving minimum re-design for different configurations becomes difficult
Solution Approach 1:
The data channels and arbitration multiplexors are designed with universal interfaces and protocols that can accommodate different numbers and configurations of LLC memory banks and CPU cores. The tileable modular design uses standardized connection patterns that allow the same basic unit to be replicated and configured in various arrangements (2 CPUs, 4 CPUs, 8 CPUs, etc.) without requiring redesign of the fundamental interconnect structure.
Data Source
AI summary
A method and apparatus are provided. The apparatus includes a plurality of central processing units, a plurality of core input/output units, a plurality of last level cache memory banks, an interconnect network comprising multiple instantiations of dedicated data channels, wherein each dedicated data channel is dedicated to a memory transaction type, each instantiation of dedicated data channels includes arbitration multiplexors, and each dedicated data channel operates independently of other data channels.