Non-Uniform Gate Electrode Thickness for Memory Integration
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Solution Overview
Problem
The integration of semiconductor memory devices is limited by the difficulty in increasing the number of gate electrode layers without causing defects such as short circuits due to the thickness of each gate electrode layer, which affects the process complexity and reliability of the memory device.
Innovation Solution
The semiconductor device employs a stack of alternating first interlayer insulating layers and gate electrode layers, with the gate electrode layers having a greater thickness only in the pad region where contacts are connected, and ion implantation is used to form sacrificial layer removal spaces, allowing for increased integration and reliability by preventing contacts from penetrating through the gate electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of gate electrode layers is increased to improve integration, then the device capacity increases, but the thickness of each gate electrode layer decreases causing contacts to penetrate through and create short circuits
Solution Approach 1:
The gate electrode layers are designed with non-uniform thickness, being thicker in the pad region where contacts are formed and thinner in the channel region. This local variation in thickness allows contacts to reliably connect to gate electrodes without penetrating through to adjacent layers, resolving the short circuit issue while maintaining high integration
Solution Approach 2:
The patent transitions from a two-dimensional planar transistor structure to a three-dimensional vertical transistor structure with stacked gate electrode layers. This dimensional change enables increased integration capacity while the varying thickness in the vertical dimension prevents contact penetration and short circuits
2Quantity of substance
If the number of gate electrode layers is increased to improve integration, then the device capacity increases, but the process complexity increases
Solution Approach 1:
The gate electrode structure is segmented into multiple thin layers stacked vertically, with each layer having different thickness characteristics. This segmentation allows the complex multi-layer structure to be manufactured using standard thin-film deposition techniques, managing process complexity while achieving high integration
Solution Approach 2:
The patent employs parameter changes in the deposition process to create gate electrode layers with varying thickness profiles. By controlling deposition parameters such as deposition rate, temperature, and layer composition, the desired non-uniform thickness is achieved without requiring additional complex processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration and reliability of the memory device by allowing a greater number of gate electrode layers to be stacked without increasing process complexity, while mitigating defects like short circuits, thereby improving the device's capacity and performance.
Implementation Method 1
implanting ions through at least one of the landing portions to an interface between a bottom surface of the at least one landing portion and one of the first interlayer insulating layers under the at least one landing portion
Data Source
AI summary
In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.