Non-Uniform Gate Insulating Layer for Memory Edge Reliability
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Solution Overview
Problem
In non-volatile memory devices, the interface trap density at the edge of the active region increases due to lattice damage, leading to reduced reliability and operating speed as the device becomes highly integrated, and edge-thinning of the tunnel insulating layer concentrates the electric field, causing charge trapping and threshold voltage dispersion.
Innovation Solution
The method involves forming first and second device isolation regions on a semiconductor substrate to define a semiconductor active region, with a spacer insulating layer and a non-uniformly thick gate insulating layer, including a charge trap layer and a charge blocking layer, to support the formation of a charge-trap type non-volatile memory device, which helps in reducing edge-thinning and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform thickness gate insulating layer is formed, then the manufacturing process is simple, but edge-thinning occurs and reliability decreases
Solution Approach 1:
The patent applies local quality by forming a non-uniform gate insulating layer where the thickness varies across different regions. Specifically, the gate insulating layer has a first thickness in the first region and a second thickness in the second region, with the second thickness being greater than the first thickness. This local variation in thickness addresses the edge-thinning problem by providing enhanced insulation at critical edges while maintaining manufacturing feasibility through selective deposition processes.
2Manufacturing precision
If the tunnel insulating layer thickness is reduced at edges, then manufacturing precision is improved, but electric field concentration increases causing charge trapping
Solution Approach 1:
The patent applies parameter changes by deliberately varying the thickness parameter of the gate insulating layer across different spatial regions. The gate insulating layer thickness is changed from a first thickness in the first region to a second thickness in the second region. This parameter variation resolves the contradiction by maintaining sufficient thickness at edges to prevent electric field concentration while allowing thinner regions where needed for manufacturing precision.
3Productivity
If device integration is increased, then productivity is improved, but interface trap density increases reducing operating speed
Solution Approach 1:
The patent applies local quality by implementing region-specific gate insulating layer thickness control in highly integrated devices. The non-uniform thickness distribution (first thickness in first region, second thickness in second region) addresses local variations in electric field distribution that occur in high-density integration, preventing interface trap formation at critical edges while maintaining overall device integration and operating speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the edge-thinning effect and enhances the reliability of non-volatile memory devices by maintaining a thicker gate insulating layer at the edges, thereby improving the operating speed and reducing charge trapping, leading to better integration and performance.
Implementation Method 1
a non-uniformly thick gate insulating layer is then formed by depositing a second insulating layer on the exposed portion of the semiconductor active region and on the residues of the first insulating layer
Data Source
AI summary
Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.