Non-Uniform Gate MOS Transistor Cell Library for Leakage Reduction
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Solution Overview
Problem
Standard cell libraries in MOS technology face challenges with MOS transistors of minimum dimensions achieving high operating speed but resulting in high leakage currents, leading to increased integrated circuit consumption and complexity in synthesis due to varying cell sizes.
Innovation Solution
A standard cell library is developed with two cell definitions for each component: one optimizing transistor operating speed and another optimizing electric consumption, both taking up the same surface area, where the latter has longer gate lengths only on either side of the central portion to reduce leakage current without increasing overall surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MOS transistors of minimum dimensions are used, then operating speed is improved, but leakage current increases
Solution Approach 1:
The gate length is made non-uniform along its length: the central portion has the minimum gate length Lmin for high speed operation, while the lateral portions have extended gate lengths for reduced leakage current. This local variation in gate length allows different sections of the same transistor to serve different functional purposes.
Solution Approach 2:
The gate structure is segmented into distinct portions with different lengths: a central portion of length Lmin and lateral portions of extended length. This segmentation allows the transistor to simultaneously achieve high speed in the central region and low leakage at the edges.
2Loss of energy
If gate length is increased to reduce leakage current, then leakage current is reduced, but surface area increases
Solution Approach 1:
The gate length extension is applied locally only to the lateral portions of the gate that are not directly above the active channel region. The central portion maintaining minimum length ensures compact area, while the extended lateral portions provide leakage reduction without proportionally increasing the active area.
3Adaptability or versatility
If different cell sizes are used to optimize for speed vs. consumption, then performance is improved, but synthesis complexity increases
Solution Approach 1:
A single standardized cell design incorporates the non-uniform gate structure that can simultaneously provide both high-speed and low-leakage performance characteristics. This universal cell can be used in various circuit contexts without requiring separate cell libraries for different performance optimizations.
Data Source
AI summary
A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion.