Non-Vertical Through-Vias for High-Density I/O Redistribution
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in increasing I/O pad density due to smaller die sizes, leading to limitations in fan-in packages and potential solder bridges, while fan-out packages can redistribute I/O pads but require complex processes and may suffer from delamination issues.
Innovation Solution
The method involves forming through-vias with non-vertical profiles, such as sand timer, mushroom, or tapered shapes, which increase the top area and interface with redistribution lines, reducing stress and delamination likelihood, and allowing for increased I/O pad density through redistribution and efficient packaging processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fan-in package is used to maintain smaller die size, then manufacturing cost is reduced and throughput is increased, but the number of I/O pads is limited due to pitch constraints and solder bridge risks
Solution Approach 1:
The patent transitions from a planar 2D pad layout to a 3D vertical architecture by introducing through-vias that extend downward from the die surface. This allows I/O pads to be distributed both on the surface and within the vertical structure, effectively increasing the number of I/O pads without increasing the die footprint area.
Solution Approach 2:
The patent embeds through-vias within the die structure, creating a nested configuration where conductive pathways are contained within the die body. This nesting approach allows additional I/O connections to be integrated inside the die volume, increasing I/O density without expanding the external dimensions.
2Quantity of substance
If I/O pad pitch is decreased to increase pad density, then more I/O pads can be packed, but solder bridges may occur
Solution Approach 1:
By moving from a 2D surface-only pad arrangement to a 3D structure with through-vias extending vertically, the patent increases spatial separation between adjacent I/O pads. This vertical dimension provides additional clearance that prevents solder bridges while still achieving high pad density within the same footprint.
3Quantity of substance
If fan-out package is used to redistribute I/O pads to greater area, then I/O pad density can be increased, but process complexity increases and delamination issues may occur
Solution Approach 1:
The patent applies local quality by creating through-vias only in specific regions where I/O redistribution is needed, rather than uniformly across the entire die. This localized approach increases I/O density where required while maintaining simpler processes in other areas, reducing overall process complexity.
4Reliability
If through-vias with non-vertical profiles are formed to increase top area and interface with redistribution lines, then stress and delamination likelihood are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs curved or tapered via profiles instead of straight vertical walls. This curvature provides a gradual transition in cross-sectional area, which reduces stress concentration at the via-top interface and improves bonding with redistribution lines, thereby enhancing delamination resistance.
Data Source
AI summary
A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.