Non-Volatile Memory Device Fowler-Nordheim Tunneling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile memory devices face issues with the bird beak effect from shallow trench isolation structures and high power consumption due to high voltage requirements for programming and erasing operations, necessitating an improved memory cell design for faster and more reliable operations.
Innovation Solution
The proposed method involves a memory device with a substrate, memory cells having a gate, source, drain, channel, charge storage layer, and a multi-layer tunneling dielectric structure, where electrons or holes are injected through the multi-layer tunneling dielectric structure by Fowler-Nordheim tunneling to increase or decrease the threshold voltage, allowing for efficient programming and erasing without affecting reliability and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a shallow trench isolation structure is used, then device miniaturization is enabled, but the bird beak effect severely affects the tunneling oxidation layer and reduces reliability
Solution Approach 1:
The patent extracts the tunneling oxidation layer from the channel region and relocates it to the charge storage layer region. This separation removes the tunneling oxidation layer from the area affected by the bird beak effect of the shallow trench isolation structure, thereby eliminating the reliability issue while preserving device miniaturization benefits
Solution Approach 2:
The patent changes the spatial dimension of the tunneling oxidation layer placement from being in the channel region (affected by STI) to being in the charge storage layer region (above the channel). This dimensional relocation allows the tunneling oxidation layer to avoid the bird beak effect while maintaining its functional integrity
2Reliability
If high voltage is applied for electron tunneling programming or erasing, then programming and erasing operations can be performed, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameter from high voltage to low voltage operation by utilizing the relocated tunneling oxidation layer. The layer's new position enables effective electron tunneling at lower voltages, reducing power consumption while maintaining reliable programming and erasing operations
Solution Approach 2:
The patent substitutes the high-voltage-driven tunneling mechanism with a low-voltage tunneling mechanism enabled by the optimized tunneling oxidation layer structure and position. This substitution reduces the energy required for electron tunneling during programming and erasing operations
3Device complexity
If conventional tunneling oxidation layer structure is used, then memory cell structure is simple, but operation speed is slow
Solution Approach 1:
The patent performs preliminary action by pre-positioning the tunneling oxidation layer on the charge storage layer before the programming operation. This preliminary placement optimizes the tunneling path and reduces the time required for electron tunneling during actual programming operations, thereby increasing operation speed without complicating the overall structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the speed and reliability of memory operations by reducing the impact of the bird beak effect and lowering power consumption, while maintaining excellent endurance through efficient programming and erasing cycles.
Implementation Method 1
electrons or holes are injected through the multi-layer tunneling dielectric structure by Fowler-Nordheim tunneling to increase or decrease the threshold voltage
Data Source
AI summary
A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN to tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.


