Non-Volatile Memory Device Hole Injection Layer
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Solution Overview
Problem
Current 3-D non-volatile memory devices with U-shaped memory strings face challenges in erase operation speed and reliability due to complex erase signal waveforms and increased erase time, as well as deteriorated select gate reliability, primarily because they rely on Gate Induced Drain Leakage (GIDL) to introduce holes for data erasure.
Innovation Solution
The proposed solution involves a non-volatile memory device design with a first and second vertical channel layer, a pipe channel layer coupling these layers, and a channel layer extension part that connects the pipe channel layer to the semiconductor substrate, allowing holes to be supplied directly from the substrate during erase operations, eliminating the need for GIDL and simplifying erase signal waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GIDL is induced to introduce holes for data erasure, then erase operation can be performed, but erase time is increased and select gate reliability is deteriorated
Solution Approach 1:
The patent extracts the hole generation function from the select gate by introducing a dedicated hole injection layer between the substrate and the U-shaped channel layer. This layer is specifically designed to generate and inject holes during erase operations, separating this function from the select gate and eliminating the need for complex GIDL induction at the select gate.
Solution Approach 2:
The patent introduces a hole injection layer as an intermediary component between the substrate and the channel layer. This intermediate layer facilitates hole generation and injection during erase operations, serving as a mediator that enables the erase function without requiring complex waveforms at the select gate.
2Ease of operation
If complex erase signal waveforms are used to induce GIDL, then holes can be introduced for erasure, but device complexity increases
Solution Approach 1:
The hole injection layer is designed to automatically generate and inject holes during erase operations through its inherent properties (such as tunnel injection or thermal field emission), eliminating the need for complex external waveform control. The layer serves itself to provide the necessary holes for erasure without requiring complicated signal sequences.
3Productivity
If U-shaped channel layers are used with select gates on both ends, then memory cells can be formed in 3-D structure, but select gate reliability deteriorates due to GIDL induction
Solution Approach 1:
The patent extracts the hole generation function from the select gate by introducing a dedicated hole injection layer between the substrate and the U-shaped channel layer. This layer is specifically designed to generate and inject holes during erase operations, separating this function from the select gate and eliminating the need for complex GIDL induction at the select gate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances erase speed and improves select gate reliability by directly supplying holes from the substrate, thereby increasing the efficiency and reliability of the erase operation without the need for complex GIDL induction.
Implementation Method 1
allowing holes to be supplied directly from the substrate during erase operations
Data Source
AI summary
A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.