Non-Volatile Memory Output Block for In-Situ Neural Computing
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Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high-performance information processing due to a lack of adequate hardware technology, particularly in terms of high computational parallelism and energy efficiency, with CMOS-implemented synapses being too bulky for the required number of neurons and synapses.
Innovation Solution
Utilizing non-volatile memory arrays as synapses in artificial neural networks, where each memory cell can be individually programmed, erased, and read without affecting other cells, enabling continuous analog programming for precise tuning of synapse weights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS analog circuits are used for synapses, then computational parallelism is achieved, but the device area becomes too bulky for high-performance neural networks
Solution Approach 1:
The patent replaces CMOS analog circuits with non-volatile memory arrays to perform synaptic computations. The memory cells utilize electrical charge storage and tunneling effects instead of traditional analog circuitry, enabling compact implementation of large-scale neural network synapses while maintaining computational parallelism through array-based operations
Solution Approach 2:
The patent changes the operational parameters by using non-volatile memory cells that store synaptic weights as electrical charge states. This allows for continuous analog-like weight representation through variable charge levels, enabling precise tuning of synapse weights while occupying minimal device area compared to CMOS implementations
2Adaptability or versatility
If digital supercomputers or GPU clusters are used, then high connectivity between neurons is achieved, but energy efficiency deteriorates
Solution Approach 1:
The patent implements in-situ memory computation where the non-volatile memory array simultaneously stores synaptic weights and performs multiplication operations. This self-service approach eliminates the need for separate multiplication logic circuits, reducing energy consumption while achieving high connectivity through the memory array's inherent parallel access capabilities
Solution Approach 2:
The patent merges the storage and computation functions into a single non-volatile memory array structure. The same memory cells that store synaptic weights also perform the multiplication operation with input signals, eliminating redundant circuitry and reducing overall energy consumption compared to separate storage and processing units
3Area of stationary object
If non-volatile memory arrays are used for synapses, then device area is reduced, but additional conversion circuits (current-to-voltage and analog-to-digital) are required
Solution Approach 1:
The patent designs the non-volatile memory array to serve multiple functions: weight storage, multiplication operation, and output signal generation. The memory array's ability to directly output current signals that can be converted to voltage and then to digital values reduces the need for separate dedicated circuits, as the same memory structure performs multiple computational roles
Data Source
AI summary
In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.