Non-Volatile Memory Fabrication via Self-Aligned Buried Drain Oxide
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Solution Overview
Problem
The existing methods for fabricating non-volatile memory devices face challenges in achieving a high gate couple ratio due to misalignment and bridging issues during photolithography, leading to uneven inter-gate dielectric layers and varying gate couple ratios, which affect device performance and efficiency.
Innovation Solution
A method is developed to form a buried drain oxide layer in a self-aligned manner, omitting at least one photolithography process, thereby increasing the gate couple ratio and improving device performance by ensuring even inter-gate dielectric coverage and reducing bridging phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and etching processes are used to pattern the second conductive layer, then the floating gates can be formed, but misalignment and bridging occur leading to uneven inter-gate dielectric layers and varying gate couple ratios
Solution Approach 1:
The patent forms the buried drain oxide layer before patterning the floating gates, using it as a pre-established reference structure. This preliminary formation ensures that subsequent layers are aligned to a stable, pre-defined geometry rather than relying on multiple photolithography alignment steps, thereby preventing misalignment and bridging issues.
Solution Approach 2:
The buried drain oxide layer serves as a self-aligned structure that automatically defines the position and geometry of the floating gates. By using the oxide layer's own geometry as the alignment reference, the patent eliminates the need for external photolithography alignment, ensuring uniform gate couple ratios without bridging between adjacent gates.
2Manufacturing precision
If multiple photolithography processes are used to increase gate couple ratio, then the overlapped area between gates can be increased, but the process complexity and fabrication steps increase
Solution Approach 1:
The patent extracts and eliminates the photolithography and etching steps from the conventional multi-step patterning process. By using the buried drain oxide layer as a self-aligned structure, the method removes the need for additional photolithography processes to define the second conductive layer, thereby reducing process complexity while maintaining or improving gate couple ratio.
Solution Approach 2:
The buried drain oxide layer performs the dual function of both electrical isolation and geometric alignment reference. This self-service capability eliminates the need for separate alignment processes, reducing the total number of fabrication steps while ensuring precise gate coupling geometry.
3Ease of manufacture
If conventional photolithography alignment is used, then floating gates can be patterned, but bridging between gates occurs leading to uneven inter-gate dielectric deposition
Solution Approach 1:
The buried drain oxide layer serves as a self-aligned mask and geometric reference that automatically prevents bridging between floating gates. By using the oxide layer's physical structure as the alignment reference, the patent ensures proper separation between gates during deposition without requiring complex photolithography alignment, thereby maintaining both ease of manufacture and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, enhances the reliability and stability of the gate couple ratio, and increases the overlapped area between the floating and control gates, resulting in improved device performance and operation speed.
Implementation Method 1
performing a thermal oxidation process to oxidize the substrate exposed by the openings to form an insulating layer
Data Source
AI summary
A method for fabricating a non-volatile memory is provided. A dielectric layer, a first conductive layer, and a mask layer are formed sequentially on a substrate and then patterned to form a number of openings and floating gates. In addition, spacers are formed on the sidewalls of the openings. A source/drain region is formed in the substrate underneath each of the openings. A thermal process is performed to oxidize the substrate exposed by the opening to form an insulating layer above the source/drain region. Afterward, the mask layer is removed and an inter-gate dielectric layer is formed to cover the surface of the first conductive layer and the surface of the insulating layer. Subsequently, a second conductive layer is formed on the inter-gate dielectric layer.