Non-Volatile Memory Timing Control Across NAND Package Configurations
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Solution Overview
Problem
The time required for a memory controller to access a non-volatile memory varies depending on whether the memory includes an interface chip, leading to inefficient timing control and increased management costs due to the need for multiple sequencer codes.
Innovation Solution
The memory system adjusts the timing constraints based on the presence or absence of an interface chip in the NAND package by using a register to store different timing values and a command sequencer to execute appropriate sequences, eliminating the need for multiple sequencer codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple sequencer codes are used to accommodate different NAND package configurations, then access timing accuracy is improved, but device complexity and management costs increase
Solution Approach 1:
The patent implements a universal sequencer code that can handle both interface chip configurations and non-interface chip configurations. The sequencer reads a configuration bit from the NAND package and automatically adjusts its timing behavior based on the detected configuration, eliminating the need for multiple dedicated sequencer codes while maintaining access timing accuracy for different package types
Solution Approach 2:
The patent changes the timing parameters dynamically based on the configuration bit read from the NAND package. When the configuration bit indicates an interface chip is present, the sequencer applies one set of timing parameters; when absent, it applies another set. This parameter adaptation allows a single sequencer code to achieve precise timing control for different hardware configurations
2Reliability
If waiting time is extended to accommodate interface chip configurations, then access reliability is improved, but productivity decreases due to unnecessary waiting
Solution Approach 1:
The patent implements dynamic waiting time adjustment based on the actual NAND package configuration. The sequencer reads the configuration bit and dynamically sets the waiting period accordingly: a longer waiting time is applied when an interface chip is detected, while a shorter waiting time is applied when no interface chip is present. This dynamic adaptation ensures reliable access without imposing unnecessary delays, thereby maintaining both access reliability and productivity
Data Source
AI summary
A memory system includes a non-volatile memory and a controller. The non-volatile memory includes at least one memory chip. The controller is electrically coupled to the non-volatile memory. The controller transmits a first instruction to the non-volatile memory, and transmits a second instruction to the non-volatile memory after transmitting the first instruction. The first instruction and the second instruction form a series of sequences. In a case where the non-volatile memory satisfies a condition, the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses. In a case where the non-volatile memory does not satisfy the condition, the second instruction is transmitted to the non-volatile e memory after a second period following transmission of the first instruction elapses. The second period is different from the first period.