Non-Volatile Memory Write During DRAM Refresh Cycle
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Solution Overview
Problem
DRAM's fast write speeds and volatility require frequent refresh cycles, which can disrupt system operations, while PCM's slower write speeds and non-volatility make it less suitable as a direct replacement without improving performance.
Innovation Solution
Implementing a dual-write strategy using a fast 'soft' pulse followed by a slower 'hard' write during the refresh cycle, leveraging the PCM's non-volatility and utilizing a temporary buffer or look-up table to manage data writes, allowing PCM to intermix with DRAM without system changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCM is used as a direct replacement for DRAM, then non-volatility and power efficiency are improved, but write speed deteriorates significantly
Solution Approach 1:
The patent performs preliminary actions by writing data to a temporary buffer location in the PCM array before the refresh cycle occurs. During the refresh cycle, the data is then transferred from the buffer to the final destination. This preliminary buffering action allows the slow PCM write operation to be decoupled from the system's write operations, effectively hiding the write speed penalty while maintaining non-volatility benefits
Solution Approach 2:
The patent utilizes the periodic refresh cycles of DRAM as opportunities to perform PCM write operations. By synchronizing data transfers to occur during these periodic refresh intervals, the system converts an otherwise wasted time period into productive write time for the PCM array, thereby improving effective write throughput without compromising data reliability
2Reliability
If DRAM refresh cycles are performed frequently, then data stability is maintained, but system operations are disrupted
Solution Approach 1:
The patent merges two separate operations - DRAM refresh and PCM data writing - into a single coordinated process. By combining these operations so that PCM writes occur during DRAM refresh cycles, the system achieves both data stability (through regular DRAM refreshing) and operational continuity (by utilizing otherwise idle refresh periods for productive write operations to non-volatile memory)
Data Source
AI summary
Writing to non-volatile memory during a volatile memory refresh cycle is described. In one example, a write command is received and data is received to write into a memory cell. The data is temporarily stored in response to the write command. A refresh command is received and the temporarily stored data is written into the memory cell in response to the refresh command.