Non-Volatile Register Direct Load Mechanism
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Solution Overview
Problem
Conventional digital circuit registers and shift registers store data volitionally, requiring data to be reloaded from non-volatile memory upon power-up, leading to performance degradation and increased power consumption due to the need for data fetching from memory units.
Innovation Solution
The development of Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices that directly load non-volatile data from semiconductor memory elements into static memory elements, eliminating the need for data fetching from non-volatile memory units by using cross-connected MOSFET inverters and semiconductor non-volatile memory elements to represent and store data persistently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional registers use volatile memory elements (cross-connected inverters), then fast and constant data referencing is achieved, but data is lost when power is turned off requiring reloading from non-volatile memory
Solution Approach 1:
The patent merges volatile memory elements (cross-connected inverters for fast access) with non-volatile memory elements (charge trapping layer for data persistence) into a single register cell structure. This combination allows the register to simultaneously achieve fast data referencing when powered on and data persistence when powered off, eliminating the need to reload data from external non-volatile memory.
Solution Approach 2:
The register cell is designed to perform multiple functions: it operates as a conventional volatile register when powered on for fast data access, and as a non-volatile storage element when powered off to retain data. The same physical structure serves both purposes, eliminating the need for separate volatile and non-volatile memory components.
2Reliability
If data is reloaded from non-volatile memory units upon power-on, then data persistence is maintained, but performance degradation occurs due to data fetching time
Solution Approach 1:
The non-volatile memory elements (charge trapping layer) continuously maintain data in a trapped state even when the circuit is powered off, performing the data retention action in advance. When power is restored, the data is already prepared and immediately available in the register cells, eliminating the need for time-consuming data fetching and reloading operations.
3Reliability
If data is fetched from non-volatile memory units, then data persistence is ensured, but power consumption increases due to memory sensing circuitry
Solution Approach 1:
The patent combines the volatile register functionality with non-volatile memory elements in the same cell structure, eliminating the need for separate non-volatile memory units and their associated sensing circuitry. The charge trapping layer directly interfaces with the inverter outputs, removing the need for complex memory sensing and data transfer operations that consume power.
4Speed
If conventional registers are used with cross-connected inverters, then fast data access is achieved, but data is volatile and requires external non-volatile memory
Solution Approach 1:
The patent integrates non-volatile memory elements (charge trapping layer with tunnel oxide) directly into the register cell structure alongside the cross-connected inverters. This merger creates a unified cell that combines fast access capabilities with built-in non-volatile storage, eliminating the need for separate external non-volatile memory units and reducing overall system complexity.
Data Source
AI summary
Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.