Non-volatile Semiconductor Device with P-type Floating Gate
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the size of electronic components and increasing the stability of integrated circuits, requiring novel electronic components that can be fabricated with simpler processes to reduce production time and costs.
Innovation Solution
A non-volatile semiconductor device is designed with a gate dielectric layer, a p-type floating gate, coupling gates, and contact plugs, allowing for programming through various electrical potentials, which enables faster programming and erasing without additional thermal cycles or masks, using standard logic processes to minimize cell size and production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional component design is used, then integration density can be improved through feature size reduction, but further size reduction and stability improvement become difficult
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based transistors to metal oxide semiconductor (MOS) material with higher bandgap energy, enabling operation at lower voltages and improving stability while allowing further miniaturization without sacrificing reliability
Solution Approach 2:
The invention uses composite material structure combining metal oxide semiconductor layer with conventional semiconductor substrate, integrating the stability benefits of wide-bandgap material with the成熟的 fabrication processes of conventional silicon technology
2Manufacturing precision
If additional thermal cycles or masks are used in fabrication, then manufacturing precision can be improved, but production time and costs increase
Solution Approach 1:
The patent merges the formation of the metal oxide semiconductor layer with the existing CMOS fabrication process flow, combining multiple functions into a single integrated process that eliminates separate thermal cycles and mask steps, thereby maintaining manufacturing precision while improving productivity
Solution Approach 2:
The fabrication process is designed to be universal and compatible with standard CMOS manufacturing lines, allowing the same process equipment and procedures to produce both conventional and novel semiconductor devices without requiring dedicated specialized process steps
3Area of moving object
If component size is reduced, then integration density improves, but fabrication process complexity increases
Solution Approach 1:
The patent segments the semiconductor device into distinct functional layers (conventional substrate layer, metal oxide semiconductor layer, gate electrode layer) that can be fabricated independently using standard process modules, reducing overall fabrication complexity despite miniaturization
Solution Approach 2:
The invention transitions from planar 2D scaling to vertical 3D stacking architecture, placing the metal oxide semiconductor layer above the conventional substrate in the vertical dimension, thereby achieving higher integration density without further reducing lateral feature sizes and avoiding associated fabrication complexity
Data Source
AI summary
A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a n-type semiconductor substrate. The p-type floating gate is formed on the gate dielectric layer. The first p-type source/drain and the second p-type source/drain are formed in the n-type semiconductor substrate. The first and second contact plugs are formed on the first and second p-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer.