Non-Volatile Memory Tail-Bit Identification for In-Place Correction
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Solution Overview
Problem
Non-volatile memory systems face challenges in ensuring reliable data retrieval due to errors in threshold voltage distributions, which can lead to unsuccessful data reading, and existing designs face limitations in optimizing memory die area allocation between memory structures and peripheral circuitry.
Innovation Solution
The proposed solution involves identifying memory cells with error bits in upper and lower tails of threshold voltage distributions and adjusting their voltages to center them within the distributions, using a system that separates memory structures and peripheral circuitry onto separate dies for optimized manufacturing and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells with error bits in upper and lower tails are adjusted to center within threshold voltage distributions, then data retrieval reliability is improved, but device complexity increases due to additional control circuitry needed for identification and adjustment
Solution Approach 1:
The patent divides the memory system into separate dies: one die dedicated to memory structures and another die for peripheral circuitry including the error correction logic. This segmentation isolates the complexity of tail-bit identification and voltage adjustment circuitry to a dedicated control die, preventing it from complicating the memory array design while still achieving improved data retrieval reliability through systematic error correction
Solution Approach 2:
The patent introduces an intermediary control die that acts as a mediator between the memory structures and the host system. This intermediary contains the specialized circuitry for identifying tail bits and performing voltage adjustments, thereby handling the complexity of error correction without directly complicating the memory cell structures themselves
2Ease of manufacture
If memory structures and peripheral circuitry are separated onto separate dies, then manufacturing efficiency and functionality are optimized, but device complexity increases due to multi-die architecture
Solution Approach 1:
The patent implements physical segmentation by placing memory structures on one die and peripheral circuitry on separate dies. This segmentation enables independent optimization of each die for its specific function, simplifies manufacturing processes for each component, and allows parallel production, thereby improving overall manufacturing efficiency despite the increased system-level complexity of integrating multiple dies
Solution Approach 2:
The peripheral circuitry die is designed as a universal control unit that can manage multiple memory dies, performing functions such as tail-bit identification, voltage adjustment, and error correction across different memory structures. This multi-functionality reduces the need for dedicated control circuitry on each memory die, simplifying the overall system architecture while maintaining manufacturing efficiency
Data Source
AI summary
In response to determining that a data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails have their threshold voltages increased by bit level program. The identification of which memory cells with error bits are in upper tails and lower tails can be determined on the memory die using a series of logic operations.