Non-binary Flash Array Modular Addressing for Die Size Reduction
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Solution Overview
Problem
Conventional memory arrays with binary dimensions face limitations in flexibility and capacity, as they do not fit all package sizes and have a fixed die size aspect ratio, leading to inefficiencies in die size and spare array area usage.
Innovation Solution
Implementing a non-binary number of Physical Sectors, Physical Pages, and Erase Sector Groups in a Flash memory array, allowing for a flexible aspect ratio and increased capacity by using modular arithmetic to calculate addresses, which translates binary user addresses into non-binary physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional binary memory arrays are used, then the structure is simple and easy to manufacture, but the flexibility in package sizes and die aspect ratio is limited
Solution Approach 1:
The patent changes the fundamental parameter of memory array organization from binary (power of 2) to non-binary dimensions. Specifically, it uses 3 Physical Sectors × 3 Physical Pages × 3 Erase Sector Groups = 27 total Erase Sectors, which allows flexible adaptation to different package sizes and die aspect ratios while maintaining manufacturing feasibility through systematic address translation
2Productivity
If conventional binary memory arrays are used, then the addressing scheme is simple, but the die size and spare array area usage are inefficient
Solution Approach 1:
The patent introduces an address translation mechanism as an intermediary between the simple binary user address space and the optimized non-binary physical array structure. The controller translates user addresses (e.g., 15 bits for 32K bytes) into physical addresses that map to the 3×3×3 array structure, achieving improved layout efficiency without exposing complexity to the user
Data Source
AI summary
A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs). A user address is translated into a physical address using modular arithmetic to determine pointers (ysel, esg, psec) for specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG); a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and a given Physical Sector (PSec) within the array.