Non-Binary LDPC Decoding Without FFT Memory Overhead

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Solution Overview

Problem

Existing decoders for multi-level cell (MLC) flash memory devices are complex, computationally expensive, and require large internal memory, which affects the usability and retention of flash memory, necessitating a more efficient decoding algorithm with reduced complexity and memory requirements.

Innovation Solution

A decoding algorithm and structure that eliminates the need for fast Fourier transform (FFT) computations and reduces memory requirements by using a Min-Sum-Max (MSM) algorithm, which selects and updates confidence vectors based on check node return values, reducing memory storage needs and computational complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FFT-based decoding methods are used, then decoding performance is improved, but computational complexity and memory requirements increase significantly

Engineering Contradiction:
Improvedecoding performanceVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces expensive FFT computations with cheaper min-sum-max operations that are computationally simpler and faster to execute. The MSM algorithm uses basic arithmetic operations (min, max, sum) instead of complex Fourier transforms, significantly reducing computational complexity while maintaining acceptable decoding performance for MLC flash memory

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the mathematical parameters and operations used in decoding from FFT-based complex exponential operations to MSM-based min-sum-max operations. This parameter change transforms the decoding process into one that operates with simpler mathematical functions, reducing both computational complexity and memory requirements while preserving error correction capability

Inventive Principle:
Principle #35Parameter changes

2Reliability

If FFT-based decoding methods are used, then decoding performance is improved, but internal memory requirements increase

Engineering Contradiction:
Improvedecoding performanceVSAvoidinternal memory
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent reduces memory requirements by replacing FFT-based methods that require storing large complex arrays with MSM algorithms that operate with smaller real-valued vectors. The confidence vectors in MSM require less storage space compared to the full complex spectra required by FFT, directly reducing internal memory needs in the decoder

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Quantity of substance

If MLC technology is used, then storage efficiency is improved, but decoder complexity increases

Engineering Contradiction:
Improvestorage efficiencyVSAvoiddecoder complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies MSM algorithms specifically tailored for MLC flash memory decoding, replacing complex general-purpose FFT decoders with simplified specialized algorithms. The MSM approach uses min-sum-max operations that are computationally lighter and better suited for the specific error patterns in MLC memory, reducing decoder complexity while maintaining support for multi-bit per cell storage

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

4Quantity of substance

If MLC technology is used, then storage efficiency is improved, but retention and endurance are affected

Engineering Contradiction:
Improvestorage efficiencyVSAvoidretention and endurance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements iterative MSM decoding with confidence vector updates that provide feedback between decoding passes. The algorithm refines error correction through multiple iterations, adjusting confidence levels based on check node syndromes, which improves reliability and error correction capability for MLC memory where errors can accumulate over time and affect retention and endurance

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10298261B2Reduced complexity non-binary LDPC decoding algorithm
Publication Date: 2019.05.21 WESTERN DIGITAL TECHNOLOGIES INC
  • US10298261B2 patent drawing
  • US10298261B2 patent drawing
  • US10298261B2 patent drawing

AI summary

Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.