Non-Binary Variable Node Processing With Top-K Reliability Selection

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Solution Overview

Problem

Existing non-binary error correcting code decoders face challenges with high computational and storage resource requirements, particularly in real-time applications and systems demanding high throughput and low latency, due to the complexity of variable node processing in algorithms like the Extended Min-Sum (EMS) algorithm.

Innovation Solution

A low-complexity and low-latency variable node processing unit is implemented, which iteratively sorts and eliminates redundancy in auxiliary components to generate variable node messages, using a calculation unit and sorting and redundancy elimination unit to determine the most reliable and distinct symbols, reducing the need for extensive computational and storage resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the Extended Min-Sum (EMS) algorithm is used for decoding non-binary error correcting codes, then decoding performance approaches the Shannon limit with high spectral efficiency, but computational and storage resource requirements become prohibitively high for real-time applications

Engineering Contradiction:

Improvedecoding performanceVSAvoidcomputational and storage resource requirements

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and processes only the most reliable auxiliary components (top-k components) rather than processing all auxiliary components. This selective extraction reduces computational and storage resources while maintaining decoding performance close to the Shannon limit.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the auxiliary components by reliability metric and processes them in groups (top-k most reliable components). This segmentation allows the decoder to focus computational resources on the most important components, reducing overall complexity while maintaining high spectral efficiency.

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If all auxiliary components are processed to ensure accurate variable node messages, then decoding accuracy is maximized, but latency increases making real-time processing infeasible

Engineering Contradiction:

Improvedecoding accuracyVSAvoidprocessing latency

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by processing only the top-k most reliable auxiliary components rather than all auxiliary components. This partial processing reduces latency significantly while maintaining decoding accuracy sufficient for real-time applications.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent performs preliminary sorting and selection of auxiliary components by reliability metric before the main decoding computation. This preliminary action identifies the most important components in advance, allowing the main processing to focus only on these selected components, thereby reducing overall latency.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If extensive sorting and redundancy elimination is performed on auxiliary components, then variable node message quality is improved, but computational complexity and storage requirements increase

Engineering Contradiction:

Improvevariable node message qualityVSAvoidcomputational complexity and storage requirements

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts only the essential information from auxiliary components by selecting the top-k most reliable ones and eliminating redundant components. This extraction process improves variable node message quality by focusing on the most reliable data while reducing computational complexity and storage requirements through redundancy elimination.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS11476870B2Variable node processing methods and devices for message-passing decoding of non-binary codes

Publication Date: 2022.10.18 UNIVERSITY OF SOUTHERN BRITTANY

AI summary

Embodiments of the invention provide a variable node processing unit for a non-binary error correcting code decoder, the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit comprises:a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.