Non-Binary SAR ADC with Binary Error Correction for Faster Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional successive approximation register (SAR) ADCs are limited by their slow speed due to the need for complete settling time of voltage or charge differences, leading to increased cycle time and power consumption, especially in high-speed applications.
Innovation Solution
A novel SAR ADC architecture using an array of capacitors with binary weighted values and compensating capacitors, allowing for non-binary successive approximation with binary error correction, enabling faster sampling by stabilizing signals to the accuracy of at least two bits and using a binary-error-tolerant corrector to compensate for sampling errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complete settling time is waited for in binary approximation ADC, then measurement precision is improved, but productivity deteriorates
Solution Approach 1:
The patent applies partial settling by performing comparisons at intermediate points during the settling process rather than waiting for complete settling. The comparator performs multiple comparisons at different settling stages (e.g., after 1st, 2nd, 3rd bit settling), and the final digital output is obtained by combining these partial comparison results. This eliminates the need to wait for complete settling of all bits, thereby improving conversion speed while maintaining measurement precision.
2Productivity
If non-binary approximation method is used to tolerate sampling error, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent extracts and corrects only the specific binary errors that occur during non-binary approximation, rather than implementing a complete complex correction system. The method identifies and corrects errors in individual bits (particularly the most significant bit and other critical bits) through simplified correction logic, removing the need for extensive digital correction circuits while maintaining sampling speed advantages.
3Loss of time
If non-binary approximation is used to reduce cycle time, then loss of time is reduced, but device complexity increases
Solution Approach 1:
The patent performs partial approximation by conducting comparisons at intermediate settling stages rather than waiting for complete settling of all bits. The SAR control logic performs comparisons sequentially as bits settle (e.g., comparing after 1st bit, then 2nd bit, then 3rd bit settling), obtaining the final digital output by combining these partial results. This partial approach significantly reduces data conversion time while using only simple comparison and combination logic, avoiding complex correction circuits.
Data Source
AI summary
A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. Non-binary successive approximation register (SAR) control logic controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error.