Non-Binary SAR ADC Mode Switching for Noise-Resilient Conversion

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Solution Overview

Problem

High-performance Analog to Digital (A/D) converters face challenges in modern telecommunication receiver architectures due to increasing resolution and sampling frequency requirements, particularly in SAR converters, where thermal noise and limited bandwidth lead to comparison errors and reduced signal-to-noise ratio (SNR), exacerbated by reduced voltage supply and device degradation in scaled CMOS technologies.

Innovation Solution

A non-binary successive approximation ADC converter with dynamically adjustable noise levels, utilizing switchable capacitors and a clock divider to operate in different modes with varying noise properties, allowing for redundancy in conversion steps to compensate for thermal noise and reduce loop noise impact, thereby enhancing SNR without significant power consumption or silicon area increase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high resolution and high sampling frequency are implemented in SAR ADC converters, then conversion performance is improved, but thermal noise and loop noise increase causing comparison errors

Engineering Contradiction:
Improveconversion resolutionVSAvoidcomparison accuracy
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements dynamic switching between two operational modes (first mode with longer conversion time and lower noise, second mode with shorter conversion time and higher noise) based on the conversion step. The mode selection is controlled dynamically during the conversion process to optimize the balance between noise performance and conversion speed, directly addressing the contradiction between high resolution and noise-induced comparison errors

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the ADC by switching between different conversion modes with different noise characteristics and conversion times. The first mode uses a longer conversion time to reduce noise impact, while the second mode uses a shorter conversion time for faster operation. This parameter switching allows the system to adapt to different noise conditions and maintain comparison accuracy throughout the conversion process

Inventive Principle:
Principle #35Parameter changes

2Productivity

If conversion speed is increased to meet high sampling frequency requirements, then productivity is improved, but thermal noise and loop noise cause more comparison errors

Engineering Contradiction:
Improveconversion speedVSAvoidcomparison accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent dynamically adjusts the conversion mode based on the current conversion step and noise conditions. Early conversion steps use the first mode with longer conversion time to establish accurate initial comparisons, while later steps may use the second mode with shorter conversion time. This dynamic adjustment allows the system to maintain high overall conversion speed while ensuring comparison accuracy at critical stages

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent performs preliminary comparisons using the first mode with longer conversion time and lower noise in the initial steps. This preliminary action establishes a reliable foundation for the conversion process, allowing subsequent faster steps to proceed with confidence that the initial comparison decisions are accurate, thereby preventing error propagation

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If redundant conversion steps are added to compensate for noise, then measurement precision is improved, but conversion time increases

Engineering Contradiction:
Improvecomparison accuracyVSAvoidconversion time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies partial redundancy by adding extra conversion steps only when noise compensation is needed, rather than using full redundancy throughout the entire conversion process. The mode switching mechanism allows the system to use the first mode (with inherent noise compensation capabilities) for a portion of the conversion steps, providing just enough redundancy to correct noise-induced errors without unnecessarily extending the total conversion time

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP2555432B1Successive approximation register ADC circuits and methods
Publication Date: 2014.07.23 NXP BV
  • EP2555432B1 patent drawingFigure 1~2
  • EP2555432B1 patent drawingFigure 3
  • EP2555432B1 patent drawingFigure 4

AI summary

A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process.