Non-Blocking Bulk Memory Operations with Address-Level Conflict Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bulk memory operations cause excessive stalling and critical path latency due to blocking execution until completion, leading to increased latency and overhead, even with hardware accelerators and software synchronization.
Innovation Solution
Implement non-blocking bulk memory operations by intercepting conflicting memory accesses and ensuring the bulk memory operation associated with the conflicting target address completes before allowing the conflicting memory access to proceed, using a logic controller to expedite or block memory requests as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If blocking execution is used to ensure data integrity during bulk memory operations, then data integrity is maintained, but latency and critical path delay increase
Solution Approach 1:
The patent segments the bulk memory operation tracking into fine-grained per-address state tracking rather than blocking the entire operation. The logic controller tracks completion status of individual memory addresses independently, allowing non-segmented conflicting accesses to proceed while maintaining data integrity for addresses that are still being processed by the bulk operation.
Solution Approach 2:
The logic controller acts as an intermediary between the bulk memory operation and conflicting memory accesses. It intercepts conflicting accesses, checks the completion status of the corresponding addresses in the bulk operation, and selectively allows or blocks access based on this status, thereby mediating between data integrity requirements and latency reduction goals.
2Speed
If hardware accelerators are used for bulk memory operations, then operation speed increases, but execution remains serialized and blocking
Solution Approach 1:
The patent introduces dynamic control of memory access blocking based on real-time completion status. Instead of static blocking for the entire bulk operation duration, the logic controller dynamically adjusts access permissions address-by-address as the bulk operation progresses, enabling subsequent tasks to proceed as soon as individual addresses are completed while the hardware accelerator continues processing remaining addresses.
3Reliability
If software synchronization is implemented to track bulk operation completion, then data consistency is maintained, but computational overhead increases
Solution Approach 1:
The patent replaces complex software synchronization mechanisms with a streamlined logic controller that uses simple completion status tracking. Instead of implementing full software synchronization protocols with multiple atomic requests and fine-grain tracking, the logic controller maintains minimal per-address completion flags and uses simple comparison logic to determine whether conflicting accesses should be blocked, significantly reducing computational overhead.
Data Source
AI summary
Non-blocking processing system are described. In accordance with the described techniques, a pending range store receives, at a start of a bulk memory operation, a pending memory range of the bulk memory operation. A logic unit includes at least one of check conflict logic or check address logic. The logic unit detects a conflicting memory access based on a target address of the pending memory range conflicting with a memory access request separate from the bulk memory operation. The logic unit performs at least a portion of the bulk memory operation associated with the target address before the memory access request is allowed to proceed.