Non-blocking Control Sync in Non-volatile Memory
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Solution Overview
Problem
Data storage devices face inefficiencies in performing control sync operations, as they often require blocking other memory accesses and processes, leading to reduced throughput during the writing of updated control information to non-volatile memory.
Innovation Solution
Implementing non-blocking control sync operations by concurrently writing control information and data to non-volatile memory, using techniques such as indicating 'safe' and 'vulnerable' data and employing barrier commands to ensure accurate representation of memory states, allowing continuous memory operations without halting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control sync operations block other memory accesses to ensure data integrity, then data coherence is maintained, but throughput is reduced
Solution Approach 1:
The patent segments memory operations into control sync operations and data write operations, allowing them to proceed independently. Control sync operations update control information in non-volatile memory without blocking data write operations, and vice versa. This segmentation resolves the contradiction by enabling both data coherence (through controlled sync operations) and high throughput (through parallel data writes).
Solution Approach 2:
The patent employs preliminary actions by pre-flushing control information to non-volatile memory before data operations that depend on this control information. This ensures that control information is already written and visible to subsequent operations, eliminating the need for blocking and maintaining both coherence and throughput.
2Reliability
If control information is written to non-volatile memory during data operations, then data integrity is maintained, but memory access speed is reduced
Solution Approach 1:
The patent merges control information writes and data writes into simultaneous parallel operations. Both control information and data are written to non-volatile memory concurrently using shared memory interfaces and buffers. This merging approach maintains data integrity through coordinated writes while preserving memory access speed by eliminating sequential bottlenecks.
Solution Approach 2:
The patent introduces intermediary buffers and memory interfaces that mediate between control operations and data operations. These intermediaries allow control information to be staged and written to non-volatile memory without directly blocking data access paths, thus maintaining both integrity and speed.
3Reliability
If write operations are halted during control update, then control table coherence is ensured, but processing time is increased
Solution Approach 1:
The patent implements dynamic control over write operation scheduling, allowing the system to adaptively decide when to perform control updates based on operational state. Control updates are performed during idle periods or concurrently with data operations when coherence can be maintained, rather than statically blocking all writes. This dynamic approach ensures coherence while minimizing processing time loss.
Data Source
AI summary
An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory. The non-volatile memory is configured to store the second data and the updated control information in a non-blocking manner