Non-blocking Processor Execution via Input Buffer Mediation
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Solution Overview
Problem
Static scheduled processors face performance degradation when operations exceed their allocated execution time, leading to stalls and inefficiencies, especially when dealing with irregular latency operations.
Innovation Solution
The implementation of an apparatus and method for non-blocking execution, which includes a processor with functional units that can handle both regular and irregular latency operations, using an input buffer to store results and determine whether to output a dummy value or re-execute operations, thereby avoiding stalls and maintaining system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor stalls when an operation exceeds its allocated execution time, then the correctness of subsequent operations is maintained, but the processor performance and productivity deteriorate due to long stall cycles
Solution Approach 1:
The patent introduces an input buffer as an intermediary component between the functional unit and the operation pipeline. When extra latency occurs, the input buffer stores the intermediate result and provides a dummy value to subsequent operations, allowing the processor to continue execution without stalling while maintaining correctness through the buffer's mediation
Solution Approach 2:
The patent changes the state parameter of the input buffer from a simple storage element to a stateful component that can track whether it contains a valid result or a dummy value. This parameter change (valid vs. dummy state) enables subsequent operations to correctly handle the case where previous operations experienced extra latency
2Reliability
If the processor re-executes operations that experienced extra latency, then the correctness of results is improved, but the execution time and loss of time increases
Solution Approach 1:
The patent performs preliminary action by having the functional unit check the input buffer state before executing an operation. When the buffer contains a valid result from a previous execution, the operation is skipped, avoiding redundant execution time. This preliminary check prevents unnecessary re-execution while ensuring correctness
3Device complexity
If the processor assumes a single latency value during compilation for irregular latency operations, then the device complexity is reduced, but the measurement precision of actual latency deteriorates
Solution Approach 1:
The patent introduces dynamic adaptation at runtime to compensate for the static compilation assumption. The functional unit dynamically checks the input buffer state and adapts its execution behavior based on whether previous operations experienced extra latency, allowing the system to handle variable latency conditions without increasing compilation complexity
Data Source
AI summary
An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.