Non-coherent Interconnect for Multi-chip I/O Traffic
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Solution Overview
Problem
In multi-chip systems, the coherent interconnects used for both CPU and I/O traffic incur coherency overhead, leading to increased latency and the risk of deadlocks due to interference between CPU and I/O traffic, and require splitting larger I/O transactions into cache-line granularity, which degrades performance.
Innovation Solution
Implementing a non-coherent interconnect between SoCs to handle I/O traffic separately from CPU traffic, allowing the coherent connection to be used primarily for CPU transactions and enabling larger transaction sizes without coherency overhead, thereby reducing latency and deadlock risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a coherent interconnect is used for both CPU and I/O traffic, then data coherency is maintained, but latency increases and deadlock risk increases due to traffic interference
Solution Approach 1:
The patent segments the interconnect traffic into two separate paths: a coherent interconnect for CPU traffic requiring coherency, and an I/O interconnect for I/O traffic not requiring coherency. This segmentation allows each path to be optimized for its specific traffic type, reducing interference and latency while maintaining necessary coherency guarantees.
Solution Approach 2:
The patent extracts I/O traffic from the coherent interconnect and routes it through a separate I/O interconnect. This extraction removes the source of interference from the coherent path, allowing CPU traffic to experience lower latency while I/O traffic is handled independently without coherency overhead.
2Device complexity
If a coherent interconnect is used for both CPU and I/O traffic, then unified connection is maintained, but system performance degrades due to coherency overhead
Solution Approach 1:
The patent divides the interconnect architecture into two separate networks: a coherent interconnect for CPU-to-CPU and CPU-to-memory traffic, and an I/O interconnect for I/O device traffic. This segmentation eliminates coherency overhead for I/O operations while maintaining coherency where required, thereby improving overall system performance despite the increased structural complexity.
Solution Approach 2:
The patent changes the coherency parameter for different traffic types by routing I/O traffic through a non-coherent path. This parameter change allows I/O operations to proceed without coherency protocols, reducing overhead and improving performance for I/O-bound workloads while preserving coherency for CPU workloads.
3Reliability
If coherent connection is used for I/O transactions, then coherency is maintained, but transaction size must be limited to cache-line granularity
Solution Approach 1:
The patent extracts I/O transactions from the coherent interconnect and routes them through a separate I/O interconnect that does not enforce cache-line granularity constraints. This allows I/O operations to use larger, more efficient transfer sizes appropriate for block devices and storage, improving throughput without compromising CPU memory coherency.
Solution Approach 2:
The patent changes the transfer size parameter for I/O transactions by providing a dedicated I/O interconnect that supports larger transaction sizes unlike the coherent interconnect which is constrained to cache-line granularity. This parameter change enables more efficient bulk data transfers for I/O operations.
Data Source
AI summary
A coherent connection and a non-coherent connection are provided between system-on-chips (SoCs). The coherent connection can be coupled to coherent interconnects on the SoCs, and the non-coherent connection can be coupled to non-coherent interconnects on the SoCs. An input/output (I/O) transaction from an I/O device on a first SoC that is targeted to a second SoC can be transmitted via the non-coherent connection, and a processor transaction from the first SoC that is targeted to the second SoC can be transmitted via the coherent connection.