Non-Conformal Insulating Film Stack for FinFET Parasitic Capacitance
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Solution Overview
Problem
In FinFET devices, the integration density improvements lead to challenges in balancing the dielectric constant between trench top and trench bottom, resulting in increased RC delay and threshold voltage variation due to parasitic capacitance and device leakage issues.
Innovation Solution
A multi-layered insulating film stack is formed with a non-conformal first dielectric layer (e.g., SiN) lining the sidewalls and bottom of the opening, followed by a second dielectric layer (e.g., SiO2) with a lower dielectric constant, where the first layer is treated by a plasma process and then reduced at the bottom using a wet etch process to minimize fixed charges and optimize the dielectric stack's overall dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer dielectric structure is used to fill the trench, then the manufacturing process is simple, but the dielectric constant cannot be balanced between trench top and trench bottom, resulting in increased RC delay and threshold voltage variation
Solution Approach 1:
The single-layer dielectric structure is divided into multiple layers: a first dielectric layer (e.g., silicon nitride) and a second dielectric layer (e.g., silicon oxide) with different dielectric constants. This segmentation allows the trench to have different dielectric properties at the top and bottom regions, balancing the overall dielectric constant and reducing parasitic capacitance variation.
Solution Approach 2:
The patent uses a composite dielectric structure combining materials with different dielectric constants (e.g., silicon nitride with higher dielectric constant and silicon oxide with lower dielectric constant). This composite approach enables tailored dielectric properties in different regions of the trench, optimizing RC delay and threshold voltage uniformity.
2Ease of manufacture
If the first dielectric layer is conformal, then the deposition process is straightforward, but the parasitic capacitance is not balanced between trench top and trench bottom, leading to threshold voltage variation
Solution Approach 1:
The first dielectric layer is made non-conformal with different thicknesses at different locations: thicker at the top of the trench and thinner at the bottom. This local variation in thickness compensates for the natural capacitance gradient, balancing parasitic capacitance across the trench and reducing threshold voltage variation while maintaining manufacturing feasibility.
3Device complexity
If the dielectric layer thickness is uniform throughout the trench, then the fabrication process is simple, but the parasitic capacitance varies between trench top and trench bottom, increasing RC delay
Solution Approach 1:
The patent changes the thickness parameter of the first dielectric layer from uniform to non-uniform distribution. By making the layer thicker at the trench top and thinner at the bottom, the design optimizes the capacitive coupling at different heights, reducing overall RC delay while maintaining a relatively simple fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall dielectric constant of the insulating film stack, minimizing RC delay and threshold voltage variation while reducing device leakage by balancing parasitic capacitance across the trench.
Implementation Method 1
the first dielectric layer is treated by a plasma process
Implementation Method 2
then reduced at the bottom using a wet etch process
Data Source
AI summary
A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.