Non-Integer Clock Divider for Equispaced Multi-Phase Generation
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Solution Overview
Problem
Conventional methods for generating equispatiated phase signals, such as those used in oversampling CDR circuits, face challenges with high power consumption, large area requirements, and increased jitter due to the use of delay-locked loops and IQ dividers with multiple phase interpolators.
Innovation Solution
A low-area, low-power, all-digital solution for generating equispatiated phases from a single-phase divided clock using a high-speed clock, which employs a clock divider and a multi-phase generator that can divide the clock by non-integer factors like 1.5 or 2.5, utilizing a single-phase divided clock and its positive and negative phases to produce evenly distributed phase signals without requiring a 50% duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay-locked loop (DLL) is used to generate multiple phase signals, then equispatiated phase signals can be generated, but power consumption increases and chip area increases
Solution Approach 1:
The patent extracts only the essential function of phase generation from the complex DLL system. By using a simple counter and phase selector circuitry instead of a full DLL, it achieves the necessary phase signals without the overhead of delay elements, charge pumps, and phase detectors that consume power in traditional DLLs.
Solution Approach 2:
The patent replaces expensive, complex DLL circuitry with simpler, less costly digital logic elements such as counters and multiplexers. These simpler components consume less power and occupy less area while still achieving the required phase generation function for oversampling CDR applications.
2Reliability
If IQ divider with multiple phase interpolators is used to generate multiple phase signals, then equispatiated phase signals can be generated, but chip area increases and power consumption increases
Solution Approach 1:
The patent removes the complex IQ divider and phase interpolator structures, retaining only the essential phase selection functionality. By using a counter-based approach with simple phase selector multiplexers, it generates the required equispatiated phases without the large area footprint of traditional IQ divider architectures.
Solution Approach 2:
The patent replaces the continuous-time analog phase interpolation mechanism with a discrete-time digital counting mechanism. This substitution uses digital logic (counters and multiplexers) instead of analog delay lines and interpolators, significantly reducing the required chip area while maintaining phase accuracy.
3Reliability
If DLL is used to generate multiple phase signals, then phase locking can be achieved, but jitter increases
Solution Approach 1:
The patent extracts the phase locking function from the DLL and implements it through simple digital counter synchronization. By avoiding the delay elements and analog control circuits in DLLs that accumulate and amplify jitter, the counter-based approach maintains phase locking capability while significantly reducing jitter propagation.
Data Source
AI summary
Apparatuses and methods of widespread equispatiated phase generation of a clock divided by a non-integer factor are described. One integrated circuit includes a clock divider and a phase generator. The clock divider receives a single-phase clock signal from a clock source and generates a divided clock signal. The phase generator receives the divided clock signal and the single-phase clock signal and generates multiple phase signals using the divided clock signal and the single-phase clock signal. The phase signals are equispatiated.