Nonlinear Bitline Structures for Self-Aligned Contact Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In highly integrated semiconductor devices with small cell sizes, it is challenging to form multiple wiring lines and contacts between them without shorting, and conventional methods require exposure processes that are difficult to manage.
Innovation Solution
The semiconductor device employs nonlinear bit lines with integral spacers and conductive patterns that self-align without an exposure process, using a contact separating insulation layer to connect active areas and capacitors, allowing for the formation of buried contacts in spaces defined by the spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional exposure processes are used to form contacts between wiring lines in highly integrated semiconductor devices, then contact formation is achieved, but manufacturing complexity and difficulty increase due to the need for precise exposure operations in small cell sizes
Solution Approach 1:
The bit line structure is designed to self-align with the contact holes through its nonlinear shape and positioning, eliminating the need for separate exposure processes to define contact locations. The bit line's geometry automatically determines where contacts should be formed, making the process self-guiding and reducing manufacturing complexity.
Solution Approach 2:
The bit line is formed first with a specific nonlinear shape that pre-defines the locations where contacts will be formed. This preliminary structuring of the bit line with integrated spacers creates predetermined spaces that automatically align with contact holes, preparing the structure in advance for contact formation without requiring additional exposure steps.
2Productivity
If more wiring lines and contacts are formed in highly integrated semiconductor devices with small cell sizes, then device functionality and integration are improved, but the risk of shorting between lines and contacts increases
Solution Approach 1:
The bit line is segmented into multiple portions with different orientations and positions, creating distinct spatial zones. The nonlinear bit line structure with integrated spacers divides the contact region into separate spaces that are physically isolated, preventing shorting between adjacent contacts while maintaining high integration density.
Solution Approach 2:
The bit line is positioned at different heights relative to the substrate and word lines, creating vertical separation. The nonlinear bit line structure utilizes three-dimensional space by extending in multiple directions and at different levels, allowing contacts to be formed in spaces between bit line portions without shorting to word lines or other structures.
3Ease of manufacture
If nonlinear bit line structures with integral spacers are used to enable self-alignment, then exposure operations are minimized and manufacturing cost is reduced, but the bit line structure becomes more complex
Solution Approach 1:
The bit line and its alignment spacers are merged into a single integrated structure formed in one fabrication step. Instead of forming the bit line and spacers separately through multiple processes, they are combined into one nonlinear bit line structure with built-in spacers, reducing manufacturing steps while the added structural complexity enables self-alignment functionality.
Data Source
AI summary
Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.


