Non-linear Compression for Scan Testing Integrated Circuits
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Solution Overview
Problem
Current linear compression schemes in scan testing of integrated circuits are limited in achieving further compression beyond the number of specified bits, as they cannot exploit correlations in the test data, leading to inefficiencies in reducing the number of specified bits produced by the compressor.
Innovation Solution
A method employing non-linear data compression using multiple encoding schemes, where a random pattern generator generates data blocks encoded with bit patterns representing the coding scheme, allowing decoders to recognize and generate test vectors with reduced bit length, thereby reducing the size of the linear feedback shift register and compressor complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If linear compression schemes are used to compress test vectors, then compression efficiency is improved by exploiting don't care bits, but the number of specified bits cannot be reduced below the total number of specified bits in the test data
Solution Approach 1:
The patent changes the compression approach from linear to non-linear by introducing statistical transformations that exploit correlations in test data. The system uses probability of usage models to determine optimal compression parameters, allowing the compressor to achieve higher compression ratios by adapting to the statistical characteristics of the test data rather than using fixed linear operations.
Solution Approach 2:
The patent replaces the mechanical linear compression system with a non-linear statistical transformation system. Instead of using fixed linear operations (XOR gates, LFSR), the system employs probabilistic models and statistical analyses to compress test data, substituting the deterministic mechanical approach with a more flexible statistical one that can exploit data correlations.
2Loss of information
If non-linear statistical transformations are used to improve compression, then the number of specified bits is reduced, but the technique requires an iterative procedure that increases complexity
Solution Approach 1:
The patent performs preliminary analysis of the test data to build probability of usage models before the actual compression process. By pre-computing statistical characteristics and correlation information, the system avoids the need for complex iterative procedures during compression, instead using the pre-built models to guide the compression process efficiently.
Solution Approach 2:
The system uses feedback from statistical analysis of test data to refine compression parameters. The probability of usage models provide feedback about the actual data distribution, allowing the compressor to adjust its behavior to match real patterns in the data, thereby reducing specified bits more effectively without requiring complex iteration.
3Loss of information
If multiple non-linear encoding schemes are implemented, then compression efficiency is improved by exploiting correlations, but the device size and complexity increase
Solution Approach 1:
The patent implements a universal compression framework that can handle multiple encoding schemes through a single integrated system. The probability of usage models and statistical transformation mechanisms serve multiple functions: they compress data, exploit correlations, and adapt to different test data characteristics. This multi-functionality reduces the need for separate dedicated circuits for each compression technique.
Solution Approach 2:
The patent merges multiple non-linear encoding schemes into a unified compression system. Instead of implementing separate independent compression circuits, the system combines statistical transformations, probability models, and correlation exploitation into a single integrated approach, reducing overall device size while maintaining high compression efficiency.
Data Source
AI summary
A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector wherein at least two of the coding schemes selected for encoding are different from one another, and wherein one of the available coding schemes represents non-encoded data. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to a plurality of decoders, wherein each decoder is adapted to recognize only one of the coding schemes represented by one of the bit patterns. The decoder recognizing the coding scheme of the data block decodes the bit pattern of the data block and generates the test vectors corresponding to the data block.