Non-linear Conductor Memory with Dynamic Impedance Switching
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Solution Overview
Problem
Existing diode-based memory devices face a tradeoff between high-speed operation and low power consumption, as small resistors are needed for speed but large resistors for power efficiency, leading to inefficiencies in diode storage matrices.
Innovation Solution
The design incorporates enhancement-mode NMOS transistors as switches and diodes to dynamically control impedance, allowing for high-speed operation while minimizing power consumption by switching between high and low resistance states based on selected and non-selected rows and columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If small resistors are used in diode storage matrices, then high-speed operation is achieved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the resistance values time-dependent rather than static. Switching devices are used to dynamically change the resistance of storage elements between high and low states during different operation phases (write vs. read), allowing the system to achieve both high speed during writes and low power consumption during reads
Solution Approach 2:
The invention changes the resistance parameter of storage elements dynamically. By using switching devices to alter the resistance state of diodes or other non-linear conductors based on operation mode, the system optimizes both speed and power consumption by having different resistance values for different operational requirements
2Use of energy by moving object
If large resistors are used in diode storage matrices, then power consumption is reduced, but operation speed decreases
Solution Approach 1:
The system uses dynamic resistance switching to overcome the speed limitation. During read operations with large resistors for low power, the switching devices can temporarily reduce resistance to maintain acceptable read speeds, while during write operations the high resistance state minimizes power consumption
3Device complexity
If diodes are used for address decoding and output detection, then device complexity is reduced, but power consumption increases
Solution Approach 1:
The diode decoder circuit leverages the inherent non-linear conduction properties of diodes to perform address decoding and output detection without requiring additional active switching elements. The diodes naturally conduct only when forward-biased, providing automatic decoding functionality that reduces overall device complexity while the dynamic resistance switching manages power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient, low-power operation with improved speed and reduced power loss by effectively managing impedance through the use of NMOS transistors and diodes, optimizing the tradeoff between speed and power consumption.
Implementation Method 1
nonlinear conductive devices disposed at least at some of the storage locations... circuitry for increasing the impedance of the non-selected row switches relative to that of the selected row switch... Each nonlinear conductive element in the first array may include a diode
Data Source
AI summary
A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.