Nonlinear DCO Gain Compensation for Stable PLL Channel Hopping
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Solution Overview
Problem
Digitally controlled oscillators (DCOs) exhibit nonlinear behavior across their tuning band, leading to stability issues and uncertainty in phase locked loops (PLLs), particularly in all-digital PLLs (ADPLLs), which complicates frequency locking and signal generation.
Innovation Solution
The implementation of a compensation technique using a normalizing gain multiplier, calculated based on the DCO's nonlinear gain behavior, allows for predicting and compensating the cubic gain variation, enabling stable frequency locking and accurate clock signal generation without runtime frequency measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DCO operates across wide tuning band, then frequency range is improved, but gain nonlinearity increases causing stability issues
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gain multiplier based on the DCO's operating frequency. A frequency-dependent gain compensation mechanism is implemented where the gain parameter is modified according to the current frequency point, transforming the fixed-gain system into a variable-gain system that adapts to maintain linearity across the tuning band.
Solution Approach 2:
The patent implements feedback through a frequency detection and compensation loop. The actual DCO frequency is monitored, and based on this feedback, the gain multiplier is adjusted to compensate for nonlinearities. This closed-loop approach ensures that gain variations are continuously corrected to maintain system stability across the frequency range.
2Reliability
If DCO gain is compensated for nonlinearity, then stability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the frequency tuning band into multiple segments or regions. For each segment, a specific gain compensation value or lookup table entry is defined. This piecewise approach simplifies the overall compensation mechanism compared to implementing a continuous complex nonlinear function, reducing computational while maintaining stability.
Solution Approach 2:
The patent introduces an intermediary gain multiplier component that acts as a mediator between the frequency control input and the DCO. This intermediate element absorbs the complexity of nonlinear compensation, transforming the complex nonlinear relationship into a series of simpler linear adjustments through the gain multiplier, thereby stabilizing the system without directly complicating the core DCO structure.
3Productivity
If frequency locking is achieved rapidly, then productivity is improved, but phase error increases without compensation
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing gain compensation values in lookup tables before operation. During frequency locking, the system simply retrieves the appropriate pre-computed gain value based on the target frequency, enabling rapid locking without real-time complex calculations. This preliminary preparation maintains both speed and precision by eliminating computational delays while providing accurate phase error compensation.
Data Source
AI summary
Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.