Non-linear Film ESD Protection in PCB Substrates
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Solution Overview
Problem
Current technologies face challenges in providing effective electrostatic discharge (ESD) protection for integrated circuits, particularly in miniaturized designs, due to impractical size requirements and high resistance issues, which are exacerbated by system-level ESD events and the need for compatibility with high-performance circuits and fine-pitch devices.
Innovation Solution
A substrate with a non-linear film that switches from insulator to conductor mode at a preset voltage, featuring fine-pitched metal traces and through-holes for low-resistance pathways to ground, allowing for efficient discharge of high-stress currents and enabling miniaturization and cost-effective mass production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external protection devices are used to handle system-level ESD currents, then ESD protection capability is improved, but device area and complexity increase
Solution Approach 1:
The patent merges the ESD protection function with the existing PCB substrate structure by integrating a non-linear resistive film directly into the PCB layers. This eliminates the need for separate external protection devices while maintaining system-level ESD protection capability, thereby reducing PCB area and device complexity.
Solution Approach 2:
The PCB substrate is designed to serve multiple functions: it provides mechanical support, electrical interconnection, and integrated ESD protection through the non-linear resistive film. This multi-functionality eliminates the need for dedicated external protection components, reducing overall device area.
2Area of stationary object
If on-chip protection devices are used, then device area is reduced, but resistance increases making high-current discharge problematic
Solution Approach 1:
The non-linear resistive film is positioned specifically at strategic locations within the PCB where ESD events are most likely to occur, such as near connectors and interface pins. This localized placement provides effective ESD protection with minimal area occupation while maintaining low resistance for high-current discharge through the film's non-linear characteristics.
Solution Approach 2:
The non-linear resistive film exhibits parameter changes based on voltage stress: at normal operating voltages, it maintains high resistance to minimize leakage current, but under ESD stress conditions, its resistance drops dramatically to enable high-current discharge. This dynamic parameter change resolves the contradiction between low area and high current discharge capability.
3Reliability
If conventional ESD protection structures are used, then protection is provided, but capacitance and leakage increase affecting high-performance circuits
Solution Approach 1:
The non-linear resistive film maintains high resistance at normal operating voltages, minimizing leakage current and capacitance effects on high-performance circuits. Under ESD stress conditions, the film's resistance drops to provide effective protection. This voltage-dependent parameter change enables ESD protection without degrading circuit performance during normal operation.
4Area of stationary object
If miniaturization is pursued, then device size is reduced, but intrinsic transistor capability to handle ESD currents decreases
Solution Approach 1:
The patent uses a composite structure combining the PCB substrate with a non-linear resistive film material. This composite approach provides enhanced ESD current handling capability at the PCB level, compensating for the reduced intrinsic transistor capability in miniaturized devices, thereby maintaining reliability while pursuing miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides ultra-low resistance pathways for high-current discharge, reducing the risk of damage from system-level ESD events while minimizing PCB area and production costs, and is suitable for fine-pitched devices and high-performance circuits.
Implementation Method 1
A substrate with a non-linear film that switches from insulator to conductor mode at a preset voltage
Data Source
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AI summary
A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242) . Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events (ESD,EOS).