Non-linear Interconnect Surface for Semiconductor Joint Reliability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor devices with fine interconnect pitches, the linear contact surface area between conductive layers and bumps is susceptible to cracking, leading to joint reliability issues due to reduced contact area.

Innovation Solution

A method is developed to form a non-linear interconnect layer with an extended length by creating a substrate with a conductive layer and an insulating layer, where the conductive layer is formed within openings of the insulating layer, providing additional contact surface area through side and horizontal surfaces, reducing the likelihood of cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If linear contact surface is used between conductive layer and bump, then manufacturing process is simple, but joint reliability deteriorates due to reduced contact area and susceptibility to cracking

Engineering Contradiction:
Improvejoint reliabilityVSAvoidinterconnect layer geometry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive layer is formed with a non-linear, curved contact surface instead of a straight linear contact. This curvature increases the contact area between the conductive layer and the bump, distributing mechanical stress more effectively and reducing susceptibility to cracking, thereby improving joint reliability without significantly complicating the manufacturing process

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

The contact interface is extended from a one-dimensional linear contact to a two-dimensional non-linear contact surface by introducing lateral extension and curvature. This dimensional expansion increases the contact area between the conductive layer and bump, enhancing joint reliability while maintaining manufacturing feasibility

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If fine interconnect pitch is used, then device density and I/O count increase, but contact area between conductive layer and bump is reduced leading to cracking

Engineering Contradiction:
ImproveI/O countVSAvoidjoint reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By forming the conductive layer with a curved, non-linear contact surface, the contact area is maximized within the constrained fine pitch dimensions. This curvature allows the contact interface to wrap around the bump, increasing the effective contact area and improving joint reliability even when the overall interconnect pitch is reduced to achieve higher I/O counts

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Reliability

If contact area between conductive layer and bump is increased, then joint reliability improves, but manufacturing complexity increases

Engineering Contradiction:
Improvejoint reliabilityVSAvoidconductive layer formation
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The non-linear, curved contact surface is formed using standard photolithography and etching processes, making the manufacturing approach practical. The curvature is achieved through patterned etching of the conductive layer to create a stepped or tapered profile that increases contact area without requiring complex additional manufacturing steps

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

The conductive layer is segmented into multiple levels or steps, creating a non-linear contact surface with increased area. This segmentation is achieved through multi-layer patterning and etching processes that are already standard in semiconductor manufacturing, allowing the contact area to be increased while maintaining ease of manufacture

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9117812B2Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
Publication Date: 2015.08.25 STATS CHIPPAC MANAGEMENT PTE LTD
  • US9117812B2 patent drawing
  • US9117812B2 patent drawing
  • US9117812B2 patent drawing

AI summary

A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.