Non-linear Memory Failure Analysis Using Segmented Bitmaps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory capacity increases, the size of the failure bitmap and the time required for memory testing and repair also increase, making it difficult to detect failures that affect multiple rows and columns in conventional linear tests, leading to higher costs and longer test times.
Innovation Solution
A memory failure analysis method using a memory test apparatus that alternates between storing and compressing failure information using first and second failure detectors, allowing for both linear and non-linear test algorithms to reduce the memory required for failure bitmaps and detect failures more efficiently, with a failure accumulator capable of storing row and column redundancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity of MUT increases, then the data storage capacity increases, but the size of failure bitmap increases and test time increases
Solution Approach 1:
The patent divides the failure bitmap into multiple smaller bitmaps, each corresponding to a specific test area. Instead of using one large failure bitmap for the entire memory, the system creates separate bitmaps for different regions, reducing the size of each individual bitmap and thereby reducing the time required to write and read failure data from each bitmap.
Solution Approach 2:
The patent introduces a new dimension by mapping failure addresses to a two-dimensional failure accumulator structure with rows and columns. This allows the system to organize and compress failure information in a structured manner, enabling more efficient storage and retrieval of failure data compared to traditional linear bitmap approaches.
2Quantity of substance
If the memory capacity of MUT increases, then the data storage capacity increases, but the redundancy analysis time increases
Solution Approach 1:
The patent segments the redundancy analysis process by dividing the failure accumulator into multiple rows and columns, each corresponding to specific redundancy resources. This segmentation allows the system to analyze and repair failures in smaller, more manageable units rather than processing the entire memory array at once, thereby reducing the overall redundancy analysis time.
Solution Approach 2:
The patent applies partial action by focusing redundancy analysis only on the specific rows and columns where failures are detected, rather than analyzing the entire memory structure. The failure accumulator is updated selectively based on detected failures, enabling the system to perform redundancy analysis only where needed, thus reducing unnecessary processing time.
3Ease of operation
If conventional linear test algorithms are used, then the test process is simple, but failures affecting multiple rows and columns are difficult to detect
Solution Approach 1:
The patent transitions from linear one-dimensional test algorithms to two-dimensional non-linear test algorithms that systematically test multiple rows and columns. The failure accumulator is structured with both rows and columns, enabling the detection of failures that affect multiple lines through a structured two-dimensional approach, thereby improving failure detection capability while maintaining operational simplicity.
Solution Approach 2:
The patent applies preliminary action by pre-establishing the failure accumulator structure with rows and columns before testing. This pre-organized structure enables the system to efficiently detect and record failures affecting multiple rows and columns during testing, as the accumulator is already configured to accommodate such failures in a structured manner.
4Loss of information
If a large failure bitmap is used, then all memory addresses can be tracked, but the memory required for failure bitmap increases
Solution Approach 1:
The patent segments the large failure bitmap into multiple smaller bitmaps, each corresponding to a specific test area. This segmentation reduces the memory required for each individual failure bitmap while maintaining the ability to track all memory addresses through the collection of smaller bitmaps, thereby reducing overall memory requirements while preserving complete failure address tracking capability.
Solution Approach 2:
The patent extracts only the necessary failure information into the failure accumulator structure, separating essential failure address data from the complete bitmap. By taking out and storing only the critical failure information in the structured accumulator, the system reduces memory requirements while maintaining comprehensive failure tracking capability.
Data Source
AI summary
The present embodiment relates to a memory failure analysis method that is performed by a memory test apparatus. The memory failure analysis method includes setting a test area of a memory under test (MUT), inputting a test pattern to the set test area, receiving a test result from the MUT, and an updating operation including operation (a) of storing failure information extracted from the test result and operation (b) of compressing, updating, and storing failure information, which is stored in a failure accumulator, using the stored failure information, wherein a first failure detector and a second failure detector alternately perform operation (a) and operation (b), and the test area is a non-linear area.