Non-linear Power Gate Contacts for Current Crowding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-frequency processors, current crowding at the power gate ring border exceeds the current limits of C4 electrical contact bumps, limiting design performance and requiring either reduced circuit block current or increased design complexity through distributed power gating.
Innovation Solution
A power gate with a series of electrical contacts arranged in a substantially non-linear profile along the periphery of an integrated circuit block, providing increased contact density and improved current throughput by distributing current more effectively across the power gate boundary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ring of power gate transistors is placed around the periphery of an integrated circuit block, then power gating capability is achieved, but current crowds at the power gate ring border and exceeds the current limits of the C4 electrical contact bumps
Solution Approach 1:
The patent applies a non-linear contact profile with curved or zigzag arrangement of electrical contacts around the periphery of the integrated circuit block, replacing a simple linear rectangular arrangement. This curved configuration increases the effective perimeter length available for contacts, distributing current more evenly and increasing contact density without creating current crowding hot spots at corners or edges.
Solution Approach 2:
The patent transitions from a one-dimensional linear contact arrangement to a two-dimensional non-linear contact profile that utilizes the available peripheral space more effectively. By arranging contacts in a curved or zigzag pattern rather than a straight line, the design increases the contact perimeter and distributes current across a larger effective area, resolving the current crowding issue.
2Reliability
If the maximum current of the circuit block is limited to prevent current crowding, then current limits of C4 contact bumps are respected, but the performance of the circuit block is limited and the regions where ring style power gating can be used are restricted
Solution Approach 1:
The non-linear contact profile increases the effective perimeter length for current distribution, allowing higher total current throughput while maintaining acceptable current density at each contact point. This enables the circuit block to operate at higher performance levels without exceeding C4 contact bump current limits.
Solution Approach 2:
By utilizing a two-dimensional non-linear contact arrangement instead of a one-dimensional linear arrangement, the patent increases the available contact perimeter and distributes current more effectively, enabling higher overall current capacity and circuit performance while complying with contact current limits.
3Object-affected harmful factors
If integrated power gating is used to distribute power gates throughout the integrated circuit block, then current distribution is improved, but design complexity increases and significant additional design time is required
Solution Approach 1:
The patent segments the power gating function into a ring of transistors placed only at the periphery of the integrated circuit block, rather than distributing power gates throughout the entire block. This segmentation maintains effective current distribution by concentrating the gating function at the boundaries where current enters and exits, significantly reducing design complexity while achieving the desired current distribution effect.
Solution Approach 2:
The peripheral ring of power gate transistors serves multiple functions: it provides power gating control, distributes current effectively along the periphery, and defines the active region boundary. This multi-functional approach eliminates the need for additional distributed power gates throughout the block, reducing design complexity while maintaining current distribution benefits.
Data Source
AI summary
A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.