Non-Linear Power Rail Layout for Short-Safe IC Contacts
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) shrink in size, the decreasing gaps between power rails and other electronic components increase the risk of shorting, while attempts to reduce power rail size lead to increased resistance and speed degradation.
Innovation Solution
The implementation of a conductive via feature with an S-curved shape, which includes tilted edges, is used to connect intended conductive contact features with sufficient contact area while maintaining clearance from unintended features, achieved through a method that modifies the IC design to meet manufacturing rules by iteratively adding or abstracting polygons to ensure overlapping and spacing targets are met.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If power rail size is reduced to maintain smaller IC dimensions, then IC size is reduced, but resistance increases and speed degrades
Solution Approach 1:
The patent transitions from planar power rail design to three-dimensional non-linear power rails that extend vertically through multiple interconnect layers. This dimensional change allows power distribution without increasing lateral footprint, thereby maintaining small IC size while providing sufficient conductive path area to limit resistance and preserve signal speed.
Solution Approach 2:
The power rails are nested within the IC structure by routing them through existing interconnect layers and utilizing vertical space between layers. This nesting approach integrates power distribution into the multi-layer architecture without adding lateral bulk, enabling reduced IC size while maintaining adequate power rail dimensions for acceptable resistance.
2Volume of moving object
If power rail size is reduced to maintain smaller IC dimensions, then IC size is reduced, but shorting risk increases
Solution Approach 1:
By moving power rail routing to the vertical dimension across multiple layers, the patent increases spatial separation between power rails and other components in the lateral plane. This dimensional separation reduces the risk of shorting while maintaining compact IC footprint.
Solution Approach 2:
The patent introduces intermediate structures including insulation layers and barrier features between power rails and adjacent components. These intermediary elements provide electrical isolation and prevent shorting, enabling reduced IC size without compromising reliability.
3Reliability
If non-linear power rails are implemented, then connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs dynamic design rules and algorithms that adaptively generate non-linear power rail paths based on specific IC layout requirements. This dynamic approach allows standardized manufacturing processes to produce customized non-linear configurations, reducing the impact of increased design complexity on manufacturing.
Solution Approach 2:
The patent changes the geometric parameters of power rails from linear to non-linear configurations, allowing flexible routing that improves connection reliability. These parameter changes are implemented through modified design rule checks and automated layout tools that work within existing manufacturing capabilities, thereby limiting the increase in manufacturing complexity.
Data Source
AI summary
The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having a first pattern layer that includes first source/drain (S/D) contacts and second S/D contacts, the first and second S/D contacts are spaced away from each other by a spacing along a first direction, and each of the first and second S/D contacts have elongated shapes extending lengthwise in a second direction perpendicular to the first direction. The method includes constructing a conductive feature on a second pattern layer of the IC layout, the conductive feature having an initial rectangular shape with a length and a width, the length extending along the first direction. And the method includes modifying the conductive feature to form a modified conductive feature that is overlapped with the first S/D contacts and distanced away from the second S/D contacts.