Non-Ohmic Device Memory Cell Leakage Reduction
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Solution Overview
Problem
Conventional memory devices experience current leakage through the channel region, leading to data loss, particularly in access transistors with vertically-extending channel regions, due to polycrystalline silicon's grain boundaries and intergranular defects, which worsens gate-induced drain leakage and other leakage mechanisms.
Innovation Solution
Incorporating a non-ohmic device between the source/drain region and the capacitor of a memory cell, which changes conductivity in response to a threshold voltage or current, thereby alleviating leakage by selectively controlling the electrical coupling of the source/drain regions through a gate-induced electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory devices use access transistors with vertically-extending channel regions, then integration density is improved, but current leakage through grain boundaries and intergranular defects increases
Solution Approach 1:
A non-ohmic device is introduced as an intermediary component between the access transistor and the storage capacitor. This device acts as a mediator that selectively controls current flow, allowing signal transmission during read/write operations while blocking leakage currents through the channel region, thus resolving the contradiction between high integration density and current leakage prevention
Solution Approach 2:
The non-ohmic device changes its electrical parameters (resistance/conductivity) in response to applied voltage or current. It transitions from a high-resistance state during normal operation to a low-resistance state during active read/write cycles, dynamically adapting to operational requirements and preventing leakage without sacrificing integration density
2Reliability
If non-ohmic devices are incorporated between source/drain region and capacitor, then current leakage is reduced, but device complexity increases
Solution Approach 1:
The leakage prevention function is extracted from the access transistor itself and implemented in a separate non-ohmic device. This separation allows the access transistor to maintain its simple vertical channel structure for high integration density, while the non-ohmic device handles the complex leakage control function independently
3Reliability
If non-ohmic device maintains high resistivity to prevent leakage, then data retention is improved, but signal strength during read/write operations may be reduced
Solution Approach 1:
The non-ohmic device dynamically changes its resistance state based on operational requirements. During idle periods, it maintains a high-resistance state to prevent leakage and preserve data. During active read/write operations, it transitions to a low-resistance state to enable strong signal transmission, thus resolving the contradiction between data retention and signal strength
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The non-ohmic device effectively reduces or eliminates current leakage, enhancing data retention and reliability by maintaining high resistivity until a threshold voltage is reached, allowing for controlled conductivity and improved memory cell performance.
Implementation Method 1
The non-ohmic device has a high-resistivity (low-conductivity) mode within a region 2 of the curve where the current increases slowly with increases in voltage, and has a low-resistivity (high-conductivity) mode within a region 4 of the curve where the current increases rapidly with increases in voltage
Implementation Method 2
changes conductivity in response to a threshold voltage or current, thereby alleviating leakage by selectively controlling the electrical coupling of the source/drain regions through a gate-induced electric field
Data Source
AI summary
Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.